STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 89

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VIII - INTERNAL REGISTERS (continued)
U,V,W,Z : These four bits define the different signals delivered by the MHDLC.
Memory
P1 E0/1 : PRIORITY 1 for entity defined by E0/1
P2 E0/1 : PRIORITY 2 for entity defined by E0/1
P3 E0/1 : PRIORITY 3 for entity defined by E0/1
P4 E0/1 : PRIORITY 4 for entity defined by E0/1
Entity definition :
P4E1 P4E0 P3E1 P3E0 P2E1 P2E0 P1E1 P1E0
bit15
E1
0
0
1
1
First Case : the external RAM circuit is DRAM (T = 1 or S = 1)
- U defines the time Tu comprised between beginning of cycle and falling edge of NRAS :
- V defines the time Tv comprised between falling edge of NRAS and falling edge of NCAS :
- W defines the time Tw comprised between falling edge of NCAS and rising edge of NCAS :
- Z defines the time Tz comprised between rising edge of NCAS and end of cycle :
The total cycle is Tu + Tv + Tw + Tz.
The different output signals are high impedance during 15ns before the end of each cycle.
Second Case : the external RAM circuit is SRAM (T = 0 or S = 0)
- U and V define a part of write cycle for SRAM : the time Tuv comprised between falling edge
- W and Z define a part of read cycle for SRAM : the time Twz comprised between falling edge
N.B. The different output signals are high impedance during 15ns before the end of each cycle. On the outside of each (DRAM
or SRAM) cycle all the outputs are high impedance or not in accordance with MBL bit (see ”MBL : Memory Bus Low
impedance”).
U = 1, Tu = 60ns - U = 0, Tu = 30ns
V = 1, Tv = 60ns - V = 0, Tv = 30ns
W = 1, Tw = 60ns - W = 0, Tw = 30ns
Z = 1, Tz = 60ns - Z = 0, Tz = 30ns
and rising edge of NCE. The total of write cycle is : 15ns+Tuv + 15ns.
of NOE and rising edge of NOE. The total of read cycle is : Twz +30ns
V
0
0
1
1
Z
0
0
1
1
E0
0
1
0
1
Rx DMA Controller
Microprocessor
Tx DMA Controller
Interrupt Controller
W
U
0
1
0
1
0
1
0
1
After reset (E4F0)
bit8
bit7
Z
H
W
Entity
V
120ns
120ns
30ns
60ns
90ns
30ns
60ns
90ns
Twz
Tuv
U
T
S
STLC5465B
R
89/101
bit 0
REF