STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 87

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VIII - INTERNAL REGISTERS (continued)
A, E, S1 to S4: 6 bit word transmitted. Case of D=1.
PT0/1 : Status bits
VIII.23 - Transmit Monitor Address Register - TMAR (2C)H
When this register is written by the microprocessor, these different bits mean :
READ : READ MON MEMORY
MA 0/2 : TRANSMIT MONITOR ADDRESS
G0
NOB
L
FABT : FABT = 1, the current message is aborted by the transmitter.
TIV
If 8 bit microprocessor the Data (TMDR Register) is taken into account by the transmitter after writing bits
8 to 15 of this register.
Transmit Monitor Address Register (after reading)
When this register is read by the microprocessor, these different bits mean :
READ, MA0/2, G0 have same definition as already described for the write register cycle.
IDLE
EXE
bit15
bit15
0
0
: This bit defines one of two GCI multiplexes.
: NUMBER OF BYTE to be transmitted
: Last byte
: Timer interrupt is Validated
: When this bit is at ”1”, IDLE (all 1’s) is transmitted during the channel validation.
: EXECUTED
G0
G0
READ=1, READ MON MEMORY.
READ=0, WRITE MON MEMORY.
MA 0/2 :These bits define one of eight Monitor Channel if validated.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
NOB = 1, One byte to transmit.
NOB = 0, Two bytes to transmit.
L = 1, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is the last.
L = 0, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is not the
last.
TIV = 1, Time Out alarm generates an interrupt when the timer has expired.
TIV = 0, Time Out alarm is masked.
When this status bit is at ”1”, the command written previously by the microprocessor has been
executed and a new word can be stored in the Transmit Monitor Data Register (TMDR) by the
microprocessor.
When this bit is at ”0”, the command written previously by the microprocessor has not yet been
executed.
P1
0
0
1
1
MA2
MA2
MA1
MA1
P0
0
1
0
1
MA0
MA0
Primitive (or 6 bit word) has not been transmitted yet.
Primitive (or 6 bit word) has been transmitted once.
Primitive (or 6 bit word) has been transmitted twice.
Primitive (or 6 bit word) has been transmitted three times or more.
READ
READ
Nu
Nu
After reset (000F)
bit8
bit8
Nu
Nu
bit7
bit7
Nu
Nu
Primitive Status
H
Nu
Nu
TIV
TO
FABT
ABT
L
L
NOBT EXE
NOB
STLC5465B
0
87/101
IDLE
bit 0
bit 0
Nu