CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet - Page 26

• Manufacturer Part Number: CYII5SC1300AA-QDC
• Description: IC SENSOR IMMAGE COLOR 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AA-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Package Information
Pin List
The IBIS5-B-1300 image sensor has 84 pins and is packaged in a leadless ceramic carrier (LCC) package.
their functions.
Table 26. Pin List
Document #: 38-05710 Rev. *H
Notes
8. You can connect all pins with the same name together.
9. All digital input are active high (unless mentioned otherwise).
10. Tie all digital inputs that are not used to GND (inactive level).
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
P_DATA<8>
P_WR
S_CLK
S_DATA
S_EN
SER_MODE
VDDC
VDDA
GNDA
GNDD
VDDD
IF_MODE
DEC_CMD
Y_START
Y_CLOCK
LAST_LINE
X_LOAD
SYS_CLOCK
PXL_VALID
SS_START
SS_STOP
TIME_OUT
SYS_RESET
EL_BLACK
EOSX
DAC_VHIGH
DAC_VLOW
PXL_OUT1
Pin Name
[8, 9, 10]
Pin Type
Ground
Ground
Supply
Supply
Supply
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Digital input. Data parallel interface.
Digital input (active high). Parallel write.
Digital input. Clock signal of serial interface.
Digital input/output. Data of serial interface.
Digital input (active low). Enable of serial 3-wire interface.
Digital input. Serial mode enable (1 = Enable serial 3-wire).
Analog supply voltage. Supply voltage of the pixel core [3.3 V].
Analog supply voltage. Analog supply voltage of the image sensor [3.3 V].
Analog ground. Analog ground of the image sensor.
Digital ground. Digital ground of the image sensor.
Digital supply voltage. Digital supply voltage of the image sensor [3.3 V].
Digital input. Interface mode (1 = parallel; 0 = serial).
Analog input. Biasing of decoder stage. Connect to VDDA with R = 50 kΩ and decouple with
C = 100 nF to GNDA.
Digital input (active high). Start frame read out.
Digital input (active high). Line clock.
Digital output. Generates a high level when the last line is read out.
Digital input (active high). Loads new X-position during read out.
Digital input. System (pixel) clock (40 MHz).
Digital output. Generates high level during pixel read out.
Digital input (active high). Start synchronous shutter operation.
Digital input (active high). Stop synchronous shutter operation.
Digital output.
Global shutter: pulse when timeout reached. It is used to trigger SS_STOP; do not tie both
signals together.
Rolling shutter: pulse when second Y-sync appears.
Digital input (active high). Global system reset.
Digital input (active high). Enables electrical black in output amplifier.
Digital output. Diagnostic end-of-scan of X-register.
Analog reference input. Biasing of DAC for output dark level. Use this to set the output range
of DAC.
Default: Connect to VDDA with R = 0Ω.
Analog reference input. Biasing of DAC for output dark level. Use this to set the output range
of DAC.
Default: Connect to GND A with R = 0Ω.
Analog output. Analog pixel output 1.
Pin Description
CYII5SM1300AB
Table 26
lists the pins and
Page 26 of 35
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