CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet - Page 19

• Manufacturer Part Number: CYII5SC1300AA-QDC
• Description: IC SENSOR IMMAGE COLOR 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AA-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

X_REG Register (10:0)
The X_REG register determines the start position of the window
in the X-direction. In this direction, there are 640 possible starting
positions (two pixels are addressed at the same time in one clock
cycle). If sub sampling is enabled, only the even pixels are set
as starting position (for instance: 0, 2, 4, 6, 8… 638).
YL_REG (10:0) and YR_REG (10:0)
The YL_REG and YR_REG registers determine the start position
of the window in the Y-direction. In this direction, there are 1024
possible starting positions. In rolling shutter mode the YL_REG
register sets the start position of the read (left) pointer and the
YR_REG sets the start position of the reset (right) pointer. For
both shutter types YL_REG is always equal to YR_REG.
Image Core Register (7:0)
Bits 1:0 of the IMAGE_CORE register define the test mode of the
image core. Setting 00 is the default and normal operation mode.
In case the bit is set to ‘1’, the odd (bit 1) or even (bit 0) columns
are tight to the reset level. If the internal ADC is used, bits 0 and
1 are used to create test pattern to test the sample moment of
the ADC. If the ADC sample moment is not chosen correctly, the
created test pattern is not black-white-black-etc. (IMAGE_CORE
register set at 1 or 2) or black-black-white-white-black-black
(IMAGE_CORE register set at 9) but grey shadings if the sensor
is saturated.
Bits 7:2 of the IMAGE_CORE register define the sub-sampling
mode in the X-direction (bits 4:2) and in the Y-direction (bits 7:5).
The sub-sampling modes and corresponding bit setting are
given in
Amplifier Register (6:0)
DAC_RAW Register (6:0) and DAC_FINE (6:0) Register
These registers determine the black reference level at the output
of the output amplifier. Bit setting 1111111 for the DAC_RAW
Document #: 38-05710 Rev. *H
1. GAIN (bits 3:0)
2. UNITY (bit 4)
3. DUAL_OUT (bit 5)
4. STANDBY
The gain bits determine the gain setting of the output amplifi-
er. They are only effective if UNITY = 0. The gains and corre-
sponding bit setting are given in
In case UNITY = 1, the gain setting of GAIN is bypassed and
the gain amplifier is put in unity feedback.
If DUAL_OUT = 1, the two output amplifiers are active. If
DUAL_OUT = 0, the signals from the two buses are multi-
plexed to output PXL_OUT1 which connects to ADC_IN. The
gain amplifier and output driver of the second path are put in
standby.
If STANDBY = 0, the complete output amplifier is put in stand-
by. For normal use, set STANDBY to ‘1’.
Table 11
and
Table 12
on page 11.
Table 13
on page 12.
Figure 19. Parallel Interface Timing
register gives the highest offset voltage. Bit setting 0000000 for
the DAC_RAW register gives the lowest offset voltage. Ideally, if
the two output paths have no offset mismatch, the DAC_FINE
register is set to 1000000. Deviation from this value is used to
compensate the internal mismatch (see
page 12).
ADC Register (2:0)
Data Interfaces
Two different data interfaces are implemented. They are
selected using pins IF_MODE (pin 12) and SER_MODE (pin 6).
Table 19. Serial and Parallel Interface Selection
Parallel Interface
The parallel interface uses a 16-bit parallel input (P_DATA
(15:0)) to upload new register values. Asserting P_WRITE loads
the parallel data into the internal register of the IBIS5-B-1300
where it is decoded (see
bits REG_ADDR (3:0); P_DATA (11:0) data bits REG_DATA
(11:0).
Serial 3-Wire Interface
The serial 3-wire interface (or serial-to-parallel Interface) uses a
serial input to shift the data in the register buffer. When the
complete data word is shifted into the register buffer the data
word is loaded into the internal register where it is decoded (see
Figure
S_DATA (11:0) data bits REG_DATA (11:0). When S_EN is
asserted the parallel data is loaded into the internal registers of
the IBIS5-B-1300. The maximum tested frequency of S_DATA is
2.5 MHz.)
Serial 2-Wire Interface
The serial 2-wire interface is not operational in the IBIS5-B-1300
image sensor. Use the 3-wire SPI interface to load the sensor
registers.
2. GAMMA (bit 1)
3. BIT_INV (bit 2)
1. TRISTATE_OUT (bit 0)
In case TRISTATE = 0, the ADC_D<9:0> outputs are in
tri-state mode. TRISTATE = 1 for normal operation mode.
If GAMMA is set to ‘1’, the ADC input to output conversion is
linear; otherwise the conversion follows a 'gamma' law (more
contrast in dark parts of the window, lower contrast in the
bright parts).
If BIT_INV = 1, 0000000000 is the conversion of the lowest
possible input voltage, otherwise the bits are inverted.
IF_MODE
19). S_DATA (15:12) address bits REG_ADDR (3:0);
1
0
SER_MODE
Figure
X
1
19). P_DATA (15:12) address
CYII5SM1300AB
Parallel
Serial 3 Wire
Selected interface
Output Amplifier
Page 19 of 35
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