CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet

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... Marketing Part Number CYII5SM1300AB-QDC CYII5SM1300AB-QWC CYII5SC1300AB-QDC CYII5FM1300AB-QDC Cypress Semiconductor Corporation Document #: 38-05710 Rev. *H IBIS5 1.3 Megapixel CMOS Image Sensor Description The IBIS5-B-1300 is a solid state CMOS image sensor that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip. ...

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Contents Features .................................................................................. 1 Applications ........................................................................... 1 Description ............................................................................. 1 Ordering Information ............................................................. 1 Specifications ........................................................................ 3 Key Specifications ............................................................ 3 Electrical Specifications .................................................... 4 Architecture and Operation .................................................. 5 Floor Plan ......................................................................... 5 Pixel .................................................................................. 6 Image Core Operation ...

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Specifications Key Specifications Table 1. General Specifications Parameter Specifications Active pixels 1280 (H) × 1024 (V) Pixel size 6.7 µm × 6.7µm Master Clock 40 MHz Shutter type Global and rolling shutter Frame rate 27 fps at full resolution Windowing ...

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Electrical Specifications Recommended Operating Conditions Table 5. Recommended Operating Conditions Parameter Description VDDH Voltage on HOLD switches. VDDR_LEFT Highest reset voltage. VDDC Pixel core voltage. VDDA Analog supply voltage of the image core. VDDD Digital supply voltage of the image ...

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Architecture and Operation This section presents detailed information about the most important sensor blocks Figure 2. Block Diagram of IBIS5-B-1300 Image Sensor Pixel Y-left addressing Column amplifiers Analog multiplexer X-addressing Floor Plan Figure 2 shows the architecture of the IBIS5-B-1300 ...

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Pixel A description of the pixel architecture and the color filter array follows. Architecture The pixel architecture used in the IBIS5-B-1300 is a 4-transistor pixel as shown in Figure 3. Implement the pixel using the high fill factor technique as ...

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Spectral Response Curve 0.225 0.2 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 400 500 Figure 6 shows the spectral response characteristic for the IBIS5-B-1300 (CYII5SM1300AB) and the IBIS-5-BE-1300 (CYII5FM1300AB). The curve is measured directly on the pixels. It includes ...

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Electro-voltaic Response Curve 1,2 1 0,8 0,6 0,4 0 10000 Figure 7 shows the pixel response curve in linear response mode. This curve is the relation between the electrons detected in the pixel and the output signal. The ...

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Image Core Operation Image Core Operation and Signalling Figure functional representation of the image core without sub-sampling and column/row swapping circuits. Most of the signals involved are not available from the outside because they are generated by ...

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Global Shutter Supply Considerations The recommended supply voltage settings listed in used when the IBIS5-B-1300 sensor is in global shutter mode only. Table 8. Global Shutter Recommended Supply Settings Parameter Description VDDH Voltage on HOLD switches. VDDR_LEFT Highest reset voltage. ...

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X-Addressing Because of the high pixel rate, the X-shift register selects two columns at a time for readout runs at half the system clock speed. All even columns are connected to bus A; all odd columns to bus ...

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Output Amplifier Architecture and Settings The output amplifier stage is user programmable for gain and offset level. Gain is controlled by 4-bit wide word; offset by a 7-bit wide word. Gain settings are on an exponential scale. Offset is controlled ...

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Analog-to-Digital Converter The IBIS5-B-1300 has a 10-bit flash analog digital converter running nominally at 40 Msamples/s. The ADC is electrically separated from the image sensor. Tie the input of the ADC (ADC_IN; pin 69) externally to the output (PXL_OUT1; pin ...

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Nonlinear and Linear Conversion Mode—’gamma’ Correction Figure 15 shows the ADC transfer characteristic. The nonlinear (exponential) ADC conversion is intended for gamma-correction of the images. It increases contrast in dark areas and reduces contrast in bright areas. The non-linear transfer ...

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Electronic Shutter Types The IBIS5-B-1300 has two different shutter types: a rolling (curtain) shutter and a snapshot (synchronous) shutter. Rolling (Curtain) Shutter The name is due to the fact that the effect is similar to a curtain shutter of a ...

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Table 15. Internal Registers Register Bit Name 0 (0000) 11:0 SEQUENCER register 0 SHUTTER_TYPE 1 FRAME_CAL_MODE 2 LINE_CAL_MODE 3 CONT_CHARGE 4 GRAN_X_SEQ_LSB 5 GRAN_X_SEQ_MSB 6 GRAN_SS_SEQ_LSB 7 GRAN_SS_SEQ_MSB 8 KNEEPOINT_LSB 9 KNEEPOINT_MSB 10 KNEEPOINT_ENABLE 11 VDDR_RIGHT_EXT 1 (0001) 11:0 NROF_PIXELS ...

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Table 15. Internal Registers (continued) Register Bit Name 9 (1001) 6:0 DACRAW_REG 10 (1010) 6:0 DACFINE_REG 11 (1011) 2:0 ADC register 0 TRISTATE_OUT 1 GAMMA 2 BIT_INV 12 (1100) Reserved 13 (1101) Reserved 14 (1110) Reserved 15 (1111) Reserved Detailed ...

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Bits KNEE_POINT_MSB and KNEE_POINT_LSB select the on chip-generated pixel reset voltage. Bit KNEE_POINT_ENABLE set to ’1’ switches control to the right side of the image core so the pixel reset voltage (VDDR_RIGHT), selected by bits KNEE_POINT_MSB/LSB, is used. Use bit ...

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X_REG Register (10:0) The X_REG register determines the start position of the window in the X-direction. In this direction, there are 640 possible starting positions (two pixels are addressed at the same time in one clock cycle). If sub sampling ...

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Timing Diagrams Frame Rate The pixel rate for this sensor is high enough to support a frame rate of greater than 100 Hz for a window size of 640 × 480 pixels (VGA format). Considering a row blanking time of ...

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Figure 20 shows a recommended schematic for generating the basic signals and to avoid any timing problems. Figure 20. .Recommended Schematic for Basic Signals SYS_CLOCK_N Figure 21. Relative Timing of 5-Sequencer Control Signal Global Shutter: Single Slope Integration SS_START and ...

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Global Shutter: Pixel Readout Basic Operation Y_START and Y_CLOCK must change on the falling edge of the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that the pulse width is a minimum of one clock cycle for Y_CLOCK and ...

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Global Shutter: Multiple Slope Integration Use up to four different pixel reset voltages during multiple slope operation in synchronous shutter mode. This is done by uploading new values to KNEEPOINT_MSB/LSB/ENABLE before a new SS_START pulse is applied. Set bit KNEEPOINT_ENABLE ...

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Rolling Shutter Operation The integration of the light in the image sensor is done during readout of the other lines. The only difference with synchronous shutter is that the TIME_OUT pin is used to indicate when the Y_SYNC pulse for ...

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Windowing in Y-Direction Reapply the Y_START pulse after loading a new Y-pointer value into the YL_REG and YR_REG registers to load a new Y-pointer into the Y-shift-register. Every time a Y_START pulse appears, a frame calibration of the output amplifier ...

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Package Information Pin List The IBIS5-B-1300 image sensor has 84 pins and is packaged in a leadless ceramic carrier (LCC) package. their functions. [8, 9, 10] Table 26. Pin List Pin Pin Name Pin Type 1 P_DATA<8> Input Digital input. ...

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Table 26. Pin List (continued) Pin Pin Name Pin Type 29 PXL_OUT2 Output Analog output. Analog pixel output 2. Leave not connected if not used. 30 AMP_CMD Input Analog input. Biasing of the output amplifier. Connect to ...

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Table 26. Pin List (continued) Pin Pin Name Pin Type 65 ADC_OUT<3> Output Digital output. ADC data output. 66 ADC_OUT<2> Output Digital output. ADC data output. 67 ADC_OUT<1> Output Digital output. ADC data output. 68 ADC_OUT<0> Output ...

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Pad Position and Packaging Bare Die The IBIS5-B-1300 image sensor has 84 pins, 21 pins on every edge. The die size from pad-edge to pad-edge (without scribe-line) is: 10156.5 µm (x) by 9297.25 µm (y). Scribe lines take about 100 ...

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Package Drawing with Glass Document #: 38-05710 Rev. *H CYII5SM1300AB 001-07589 *A Page [+] Feedback ...

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Table 27. Side View Dimensions (see Figure Dimension Description A Glass (thickness) - mono B Cavity (depth) C Die - Si (thickness) - mono D Bottom layer (thickness) E Die attach-bondline (thickness) F Glass attach-bondline (thickness) G Imager to lid-outer ...

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Glass Lid The IBIS5-B-1300 image sensor uses a glass lid without any coatings. lid. As seen in Figure 31, the sensor does not use infrared attenuating color filter glass. Provide a filter in the optical path when using color devices. ...

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Ordering Code Information CY I Cypress Prefix I=Image Sensors IBIS5 S=Standard Process F=Thicker Epi M=Mono, C=Color Appendix A: IBIS5 Demo Kit For evaluating purposes an IBIS5 demo kit is available. The kit consists of a high-speed digital board (mother board) ...

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Document History Page Document Title: CYII5SM1300AB IBIS5 1.3 Megapixel CMOS Image Sensor Document Number: 38-05710 Orig. of Rev. ECN No. Change ** 310213 FVK *A 649064 FPW *B 1162847 FPW/ARI *C 1417584 FPW *D 2765859 NVEA *E 2786518 SHEA *F ...

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