DVI-FPDLINKII-R/NOPB National Semiconductor, DVI-FPDLINKII-R/NOPB Datasheet - Page 5

• Manufacturer Part Number: DVI-FPDLINKII-R/NOPB
• Description: EVAL BOARD FOR DS90UR905/6
• Manufacturer: National Semiconductor

Specifications of DVI-FPDLINKII-R/NOPB

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Name
BISTEN
RES[2:0]
FPD-Link II Serial Interface
DOUT+
DOUT-
Power and Ground
VDDL
VDDP
VDDHS
VDDTX
VDDIO
GND
NOTE: 1 = HIGH, 0 = LOW
The VDD (V
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DDn
18, 16, 15
Pin #
DAP
and V
31
20
19
14
17
22
30
7
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I/O, Type
O, LVDS
O, LVDS
Ground
Power
Power
Power
Power
Power
Description
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
Reserved - tie LOW
True Output.
The output must be AC Coupled with a 100 nF capacitor.
Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
Logic Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
5
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