DVI-FPDLINKII-R/NOPB National Semiconductor, DVI-FPDLINKII-R/NOPB Datasheet - Page 15

• Manufacturer Part Number: DVI-FPDLINKII-R/NOPB
• Description: EVAL BOARD FOR DS90UR905/6
• Manufacturer: National Semiconductor

Specifications of DVI-FPDLINKII-R/NOPB

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

t
t
t
t
t
t
t
t
t
t
t
Symbol
RCP
RDC
CLH
CHL
ROS
ROH
DDLT
DD
DPJ
DCCJ
IJT
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PCLK Output Period
PCLK Output Duty Cycle
LVCMOS
Low-to-High
Transition Time,
LVCMOS
High-to-Low
Transition Time,
Data Valid before PCLK – Set
Up Time,
Data Valid after PCLK – Hold
Time,
Deserializer Lock Time,
Figure 13
Des Delay - Latency,
Figure 11
Des Period Jitter
Des Cycle-to-Cycle Jitter
Des Input Jitter Tolerance,
Figure 16
Figure 14
Figure 14
Parameter
Figure 10
Figure 10
t
SSCG=OFF, 5–65MHz
SSCG=ON, 5–20MHz
SSCG=ON, 20–65MHz
V
C
V
C
V
C
= L
V
C
= H
V
to 3.6V
C
V
to 3.6V
C
SSC[3:0] = 0000 (OFF),
(Note
SSC[3:0] = 0000 (OFF),
(Note
SSC[3:0] = ON,
(Note
SSC[3:0] = ON,
(Note
SSC[3:0] = 0000 (OFF),
(Note
SSC[3:0] = OFF,
(Note
SSC[3:0] = OFF,
(Note
EQ = OFF,
SSCG = OFF,
PCLK = 65MHz
RCP
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
L
L
L
L
L
L
= 4 pF, OS_PCLK/DATA
= 4 pF, OS_PCLK/DATA
= 4 pF
= 4 pF
= 4pF (lumped load)
= 4pF (lumped load)
= t
= 1.71 to 1.89V or 3.0
= 1.71 to 1.89V or 3.0
= 1.8V,
= 3.3V
= 1.8V
= 3.3V
6)
6)
6)
6)
6)
8),
9),
TCP
Conditions
(Note
(Note
11)
11)
15
PCLK
PCLK
PCLK/RGB[7:0], HS,
VS, DE
PCLK/RGB[7:0], HS,
VS, DE
RGB[7:0], HS, VS, DE
RGB[7:0], HS, VS, DE
PCLK = 5MHz
PCLK = 65 MHz
PCLK = 5MHz
PCLK = 65 MHz
PCLK = 5MHz
PCLK = 10MHz
PCLK = 65 MHz
PCLK = 5MHz
PCLK = 10MHz
PCLK = 65 MHz
for jitter freq < 2MHz
for jitter freq > 6MHz
Pin/Freq.
15.38
0.27
0.40
Min
43
35
40
139*T
0.45
0.55
Typ
975
500
550
675
375
500
2.1
2.0
1.6
1.5
0.9
0.5
50
59
53
30
T
3
4
6
140*T
1700
1000
1250
1150
1150
Max
200
900
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57
65
60
Units
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
%
%
%
UI
UI
T
T