DVI-FPDLINKII-R/NOPB National Semiconductor, DVI-FPDLINKII-R/NOPB Datasheet - Page 31

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DVI-FPDLINKII-R/NOPB

Manufacturer Part Number
DVI-FPDLINKII-R/NOPB
Description
EVAL BOARD FOR DS90UR905/6
Manufacturer
National Semiconductor
Datasheet

Specifications of DVI-FPDLINKII-R/NOPB

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Des — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on.
If RFB is High, output data is strobed on the Rising edge of
the PCLK. If RFB is Low, data is strobed on the Falling edge
of the PCLK. This allows for inter-operability with downstream
FIGURE 27. OP_LOW Manual Set/Reset
FIGURE 26. OP_LOW Auto Set
31
devices. The Des output does not need to use the same edge
as the Ser input. This feature may be controlled by the exter-
nal pin or by register.
30102065
30102066
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