DVI-FPDLINKII-R/NOPB National Semiconductor, DVI-FPDLINKII-R/NOPB Datasheet - Page 4

• Manufacturer Part Number: DVI-FPDLINKII-R/NOPB
• Description: EVAL BOARD FOR DS90UR905/6
• Manufacturer: National Semiconductor

Specifications of DVI-FPDLINKII-R/NOPB

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Pin Name
LVCMOS Parallel Interface
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
Control and Configuration
PDB
VODSEL
De-Emph
RFB
CONFIG
[1:0]
ID[x]
SCL
SDA
DS90UR905Q Serializer Pin Descriptions
34, 33, 32, 29,
42, 41, 40, 39,
28, 27, 26, 25
38, 37, 36, 35
46, 45, 44, 43
2, 1, 48, 47,
13, 12
Pin #
10
21
24
23
11
3
4
5
6
8
9
I/O, LVCMOS
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
Open Drain
I/O, Type
w/ pull-up
I, Analog
I, Analog
Description
RED Parallel Interface Data Input Pins
(MSB = 7, LSB = 0)
GREEN Parallel Interface Data Input Pins
(MSB = 7, LSB = 0)
BLUE Parallel Interface Data Input Pins
(MSB = 7, LSB = 0)
Horizontal Sync Input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal
is limited to 2 transitions per 130 PCLKs.
Vertical Sync Input
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
Data Enable Input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal
is limited to 2 transitions per 130 PCLKs.
Pixel Clock Input
Latch edge set by RFB function.
Power-down Mode Input
PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
Differential Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is 280 mV, 560 mVp-p (typ)
De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See
Pixel Clock Input Latch Edge Select — Pin or Register Control
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
Operating Modes — Pin or Register Control
Determine the DS90UR905’s operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS90UR906, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V
Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor V
Table
4.
4
DDIO
DDIO
.
.
Table
13.