DVI-FPDLINKII-R/NOPB National Semiconductor, DVI-FPDLINKII-R/NOPB Datasheet - Page 30

• Manufacturer Part Number: DVI-FPDLINKII-R/NOPB
• Description: EVAL BOARD FOR DS90UR905/6
• Manufacturer: National Semiconductor

Specifications of DVI-FPDLINKII-R/NOPB

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Des — OP_LOW — Optional
The OP_ LOW feature is used to hold the LVCMOS outputs
(except the LOCK output) at a LOW state. The user must tog-
gle the OP_LOW Set/Reset register bit to release the outputs
to the normal toggling state. Note that the release of the out-
puts can only occur when LOCK is HIGH. When the OP_LOW
feature is enabled, anytime LOCK = LOW, the LVCMOS out-
puts will toggle to a LOW state again. The OP_ LOW strap
pin feature is assigned to output PASS pin 42.
Restrictions on other straps:
1) Other straps should not be used in order to keep RGB[7:0],
HS, VS, DE, and PCLK at a true LOW state. Other features
should be selected thru I2C.
FIGURE 25. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled
30
2) OSS_SEL function is not available when O/P_LOW is tied
H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in
TRI-STATE before PDB toggles HIGH because the OP_LOW
strap value has not been recognized until the DS90UR906
powers up.
OP_LOW and automatic reset of OP_LOW set on the falling
edge of LOCK.
of OP_LOW and manual reset of OP_LOW set. Note manual
reset of OP_LOW can only occur when LOCK is H.
Figure 26
Figure 27
shows the user controlled release of
shows the user controlled release
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