CS5345-DQZR Cirrus Logic Inc, CS5345-DQZR Datasheet - Page 36

• Manufacturer Part Number: CS5345-DQZR
• Description: IC,Data Acquisition Signal Conditioner,6-CHANNEL,24-BIT,CMOS,QFP,48PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

36
6.10.1 Clock Error (Bit 3)
6.10.2 Overflow (Bit 1)
6.10.3 Underflow (Bit 0)
6.11
6.12
6.13
Reserved
Reserved
Reserved
7
7
Interrupt Mask - Address 0Eh
Function:
The bits of this register serve as a mask for the Status sources found in the register
dress 0Dh” on page
the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence
will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Sta-
tus register.
Interrupt Mode MSB - Address 0Fh
Interrupt Mode LSB - Address 10h
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising-Edge Active
Mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling-Edge Active Mode,
the INT pin becomes active on the removal of the interrupt condition. In Level-Active Mode, the INT pin re-
mains active during the interrupt condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
Function:
Indicates the occurrence of a clock error condition.
Function:
Indicates the occurrence of an ADC overflow condition.
Function:
Indicates the occurrence of an ADC underflow condition.
Reserved
Reserved
Reserved
6
6
35. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect
Reserved
Reserved
Reserved
5
5
Reserved
Reserved
Reserved
4
4
ClkErrM
ClkErr1
ClkErr0
3
3
Reserved
Reserved
Reserved
2
2
OvflM
Ovfl1
Ovfl0
1
“Interrupt Status - Ad-
1
CS5345
UndrflM
Undrfl1
Undrfl0
DS658F2
0
0