CS5345-DQZR Cirrus Logic Inc, CS5345-DQZR Datasheet - Page 32

no-image

CS5345-DQZR

Manufacturer Part Number
CS5345-DQZR
Description
IC,Data Acquisition Signal Conditioner,6-CHANNEL,24-BIT,CMOS,QFP,48PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Datasheets
32
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
FM1
7
ADC Control - Address 04h
Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format
bit. The options are detailed in
Mute (Bit 2)
Function:
When this bit is set, the serial audio output of the both channels is muted.
High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See
page 24.
Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
FM1
DIF
0
0
1
1
0
1
FM0
6
Left-Justified, up to 24-bit data (default)
FM0
0
1
0
1
Reserved
5
I²S, up to 24-bit data
Single-Speed Mode: 4 to 50 kHz sample rates
Double-Speed Mode: 50 to 100 kHz sample rates
Quad-Speed Mode: 100 to 200 kHz sample rates
Reserved
Table 6. Functional Mode Selection
Table 7
Description
Table 7. Digital Interface Formats
DIF
and may be seen in
4
Reserved
3
“High-Pass Filter and DC Offset Calibration” on
Mode
Figure 3
Format
Mute
0
1
2
and
Figure
HPFFreeze
4.
1
Figure
3
4
CS5345
DS658F2
M/S
0

Related parts for CS5345-DQZR