PN5120A0HN/C1,518 NXP Semiconductors, PN5120A0HN/C1,518 Datasheet - Page 59

• Manufacturer Part Number: PN5120A0HN/C1,518
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1,518

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.4.4 TestPinEnReg
9.2.4.5 TestPinValueReg
Enables the pin output driver on the 8-bit parallel bus.
Table 116. TestPinEnReg register (address 33h); reset value: 80h, 10000000b
Table 117. Description of TestPinEnReg bits
Defines the values for the 7-bit parallel port when it is used as I/O.
Table 118. TestPinValueReg register (address 34h); reset value: 00h, 00000000b
Table 119. Description of TestPinValueReg bits
Bit
7
6 to 0
Bit
7
6 to 0
Access
Rights
Access
Rights
RS232LineEn
Symbol
RS232LineEn
TestPinEn
Symbol
UseIO
TestPinValue
UseIO
r/w
7
r/w
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7
Rev. 3.6 — 10 March 2011
r/w
6
Description
Set to logic 0, the lines MX and DTRQ for the serial UART are
disabled.
Enables the pin output driver on the 8-bit parallel interface.
Example:
Note: Only valid if one of serial interfaces is used.
If the SPI interface is used only D0 to D4 can be used. If the serial
UART interface is used and RS232LineEn is set to logic 1 only D0 to
D4 can be used.
Description
Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel
port in case one of the serial interfaces is used. The input/output
behavior is defined by TestPinEn in register TestPinEnReg. The value
for the output behavior is defined in the bits TestPinVal.
Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O.
Defines the value of the 7-bit parallel port, when it is used as I/O. Each
output has to be enabled by the TestPinEn bits in register
TestPinEnReg.
Note: Reading the register indicates the actual status of the pins D6 -
D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the
register TestPinValueReg is read back.
r/w
Setting bit 0 to 1 enables D0
Setting bit 5 to 1 enables D5
6
111336
r/w
5
r/w
5
r/w
4
r/w
4
TestPinValue
TestPinEn
r/w
3
r/w
3
r/w
2
r/w
2
Transmission module
© NXP B.V. 2011. All rights reserved.
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