PN5120A0HN/C1,518 NXP Semiconductors, PN5120A0HN/C1,518 Datasheet - Page 26

• Manufacturer Part Number: PN5120A0HN/C1,518
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1,518

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.1.8 Status1Reg
Contains status bits of the CRC, Interrupt and FIFO-buffer.
Table 30.
Table 31.
Bit
7
6
5
4
3
2
1
0
Access
Rights
RFFreqOK CRCOk CRCReady
Symbol
RFFreqOK
CRCOk
CRCReady
IRq
TRunning
RFOn
HiAlert
LoAlert
Status1Reg register (address 07h); reset value: XXh, X100X01Xb
Description of Status1Reg bits
7
r
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
6
r
Description
Indicates if the frequency detected at the RX pin is in the range of
13.56 MHz.
Set to logic 1, if the frequency at the RX pin is in the range
12 MHz < RX pin frequency < 15 MHz.
Note: The value of RFFreqOK is not defined if the external RF
frequency is in the range from 9 to 12 MHz or in the range from
15 to 19 MHz.
Set to logic 1, if the CRC Result is zero. For data transmission and
reception the bit CRCOk is undefined (use CRCErr in register
ErrorReg). CRCOk indicates the status of the CRC co-processor,
during calculation the value changes to ZERO, when the calculation is
done correctly, the value changes to ONE.
Set to logic 1, when the CRC calculation has finished. This bit is only
valid for the CRC co-processor calculation using the command
CalcCRC.
This bit shows, if any interrupt source requests attention (with respect
to the setting of the interrupt enable bits, see register CommIEnReg
and DivIEnReg).
Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will
decrement the TCounterValReg with the next timer clock.
Note: In the gated mode the bit TRunning is set to logic 1, when the
timer is enabled by the register bits. This bit is not influenced by the
gated signal.
Set to logic 1, if an external RF field is detected. This bit does not store
the state of the RF field.
Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
HiAlert
FIFOLength = 60, WaterLevel = 4 → HiAlert = 1
FIFOLength = 59, WaterLevel = 4 → HiAlert = 0
FIFOLength = 4, WaterLevel = 4 → LoAlert = 1
FIFOLength = 5, WaterLevel = 4 → LoAlert = 0
111336
=
5
r
(
64 FIFOLength
–
IRq
4
r
TRunning
LoAlert
)
≤
3
r
WaterLevel
=
RFOn
FIFOLength WaterLevel
2
r
Transmission module
© NXP B.V. 2011. All rights reserved.
HiAlert
1
r
≤
PN512
LoAlert
26 of 125
0
r