PN5120A0HN/C1,518 NXP Semiconductors, PN5120A0HN/C1,518 Datasheet - Page 54

• Manufacturer Part Number: PN5120A0HN/C1,518
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1,518

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
Table 99.
Table 100. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b
Table 101. Description of TPrescalerReg bits
Bit
6 to 5
4
3 to 0
Bit
7 to 0
Access
Rights
Symbol
TGated
TAutoRestart
TPrescaler_Hi Defines higher 4 bits for TPrescaler.
Symbol
TPrescaler_Lo Defines lower 8 bits for TPrescaler.
Description of TModeReg bits
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All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
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Description
The internal timer is running in gated mode.
Note: In the gated mode, the bit TRunning is 1 when the timer is enabled
by the register bits. This bit does not influence the gating signal.
Value
00
01
10
11
Set to logic 1, the timer automatically restart its count-down from
TReloadValue, instead of counting down to zero.
Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set
to logic 1.
The following formula is used to calculate f
Demot Reg is set to logic 0:
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits) (Default TPrescalEven is logic 0)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
For detailed description see
6
f
f
Description
The following formula is used to calculate f
Demot Reg is set to logic 0:
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
For detailed description see
Timer
Timer
f
f
Timer
Timer
= 13.56 MHz/(2*TPreScaler+1).
= 13.56 MHz/(2*TPreScaler+2).
111336
Description
Non gated mode
Gated by SIGIN
Gated by AUX1
Gated by A3
= 13.56 MHz/(2*TPreScaler+1).
= 13.56 MHz/(2*TPreScaler+2).
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…continued
TPrescaler_Lo
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Section 15 “Timer
Section 15 “Timer
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Timer
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Timer
2
unit”.
if TPrescalEven bit in
Transmission module
unit”.
if TPrescalEven bit in
© NXP B.V. 2011. All rights reserved.
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