PN5120A0HN/C1,518 NXP Semiconductors, PN5120A0HN/C1,518 Datasheet - Page 25

• Manufacturer Part Number: PN5120A0HN/C1,518
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1,518

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.1.7 ErrorReg
Error bit register showing the error status of the last command executed.
Table 28.
Table 29.
[1]
Bit
7
6
5
4
3
2
1
0
Access
Rights
Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.
Symbol
WrErr
TempErr
RFErr
BufferOvfl
CollErr
CRCErr
ParityErr
ProtocolErr
ErrorReg register (address 06h); reset value: 00h, 00000000b
Description of ErrorReg bits
WrErr
7
r
All information provided in this document is subject to legal disclaimers.
[1]
TempErr
Rev. 3.6 — 10 March 2011
6
r
Description
Set to logic 1, when data is written into FIFO by the host controller
during the AutoColl command or MFAuthent command or if data is
written into FIFO by the host controller during the time between
sending the last bit on the RF interface and receiving the last bit on the
RF interface.
Set to logic 1, if the internal temperature sensor detects overheating.
In this case, the antenna drivers are switched off automatically.
Set to logic 1, if in Active Communication mode the counterpart does
not switch on the RF field in time as defined in NFCIP-1 standard.
Note: RFErr is only used in Active Communication mode. The bits
RxFraming or the bits TxFraming has to be set to 01 to enable this
functionality.
Set to logic 1, if the host controller or a PN512’s internal state machine
(e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer
although the FIFO-buffer is already full.
Set to logic 1, if a bit-collision is detected. It is cleared automatically at
receiver start-up phase. This bit is only valid during the bitwise
anticollision at 106 kbit. During communication schemes at 212 and
424 kbit this bit is always set to logic 1.
Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the
CRC calculation fails. It is cleared to 0 automatically at receiver
start-up phase.
Set to logic 1, if the parity check has failed. It is cleared automatically
at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or
NFCIP-1 communication at 106 kbit.
Set to logic 1, if one out of the following cases occur:
•
•
•
•
•
Set to logic 1 if the SOF is incorrect. It is cleared automatically at
receiver start-up phase. The bit is only valid for 106 kbit in Active
and Passive Communication mode.
If bit DetectSync in register ModeReg is set to logic 1 during
FeliCa communication or active communication with transfer
speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in
case of a byte length violation.
During the AutoColl command, bit ProtocolErr is set to logic 1, if
the bit Initiator in register ControlReg is set to logic 1.
During the MFAuthent Command, bit ProtocolErr is set to logic 1,
if the number of bytes received in one data stream is incorrect.
Set to logic 1, if the Miller Decoder detects 2 pulses below the
minimum time according to the ISO/IEC 14443A definitions.
RFErr
111336
5
r
BufferOvfl
4
r
CollErr
3
r
CRCErr
2
r
Transmission module
ParityErr ProtocolErr
© NXP B.V. 2011. All rights reserved.
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r
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0
r