EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 572

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

15
UART2IntIDIntClr
15-14
UART2
EP93xx User’s Guide
31
15
Address:
30
14
29
13
28
12
RXFF:
TXFF:
RXFE:
BUSY:
DCD:
DSR:
CTS:
0x808D_001C
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Receive FIFO Full. The meaning of this bit depends on the
state of the FEN bit in the UART2LinCtrlHigh register. If
the FIFO is disabled, this bit is set when the receive
holding register is full. If the FIFO is enabled, the RXFF bit
is set when the receive FIFO is full.
Transmit FIFO Full. The meaning of this bit depends on
the state of the FEN bit in the UART2LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is full. If the FIFO is enabled, the TXFF bit
is set when the transmit FIFO is full.
Receive FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART2LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the receive
holding register is empty. If the FIFO is enabled, the RXFE
bit is set when the receive FIFO is empty.
UART Busy. If this bit is set to “1”, the UART is busy
transmitting data. This bit remains set until the complete
byte, including all the stop bits, has been sent from the
shift register. This bit is set as soon as the transmit FIFO
becomes non-empty (regardless of whether the UART is
enabled or not).
Data Carrier Detect status. This bit is the complement of
the UART data carrier detect (nUARTDCD) modem status
input. That is, the bit is “1” when the modem status input is
0.
Data Set Ready status. This bit is the complement of the
UART data set ready (nUARTDSR) modem status input.
That is, the bit is “1” when the modem status input is 0.
Clear To Send status. This bit is the complement of the
UART clear to send (nUARTCTS) modem status input.
That is, the bit is “1” when the modem status input is 0.
24
8
RSVD
23
7
22
6
21
5
20
4
RTIS
19
3
TIS
18
2
RIS
17
1
DS785UM1
MIS
16
0