EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 514

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

13
Register Descriptions
GlConfig
13-18
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
CKE
31
15
Address: 0x8006_0004 - Read/Write
Default: 0x0000_0000
Definition:
Bit Descriptions:
Shutdown
Clk
30
14
29
13
The Global configuration register contains general control and status bits. The
least-significant two bits, MRS and Initialize, are used in combination as
shown in
memory commands that are required during memory initialization. The
Synchronous Memory Busy Status bit, SMEMBust, provides the state of the
Synchronous Memory controller, and it can be monitored to determine when a
change of device configuration has taken effect.
RSVD:
CKE:
ClkShutdown:
28
12
RSVD
27
11
Table
26
10
Copyright 2007 Cirrus Logic
to allow access to otherwise unavailable synchronous
25
9
Reserved - Unknown During Read
Synchronous memory Clock Enable - Read/Write
Writing a value to this bit specifies if the enable signal that
is output on the SDCLKEN is asserted, or not:
0 - SDCLKEN is de-asserted to save power only when
there is no current access to any synchronous memory
device
1 - SDCLKEN is continuously asserted (especially useful
when booting from SyncROM or SyncFLASH device
types)
Synchronous memory Clock Shutdown - Read/Write
Writing a value to this bit specifies if the HCLK output on
the SDCLK pin is free-running or gated off:
0 - SDCLK is free-running
1 - SDCLK is gated off only when there is no current
access to any synchronous memory device
24
8
ReArb
En
23
7
RSVD
LCR
22
6
SMEM
Bust
21
5
20
4
RSVD
19
3
18
2
MRS
17
DS785UM1
1
Initialize
16
0