EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 206

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

7
7-24
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.4.9 Hardware Cursor
Frame
D18
Ctr
0
Assuming that the 3-bit input pattern that represents this 33% duty cycle grayscale is 0x2 or
010b, the values in
table. In this mode, the X locations are ignored by the grayscale generation.
The raster engine provides support for a hardware cursor. The hardware cursor has a
separate bus mastering interface that allows it’s image to be stored anywhere in memory.
Software provides a location start, reset, size, X and Y position, and two cursor colors. The
hardware loads a line at a time from memory and multiplexes the video stream data based on
the cursor values. The X and Y locations are compared to the horizontal and vertical counters
and trigger the state machine to enable the cursor output overlay.
Vert
D17
Ctr
0
Horz
D16
Ctr
0
VCNT (lines)
Table 7-9. Programming 33% Duty Cycle into the Lookup Table
base + 0x08
base + 0x28
base + 0x48
base + 0x68
Register
address
(pixels)
HCNT
Table 7-9
Frame 0
Frame 2
V
E
R
T
Figure 7-8. Three and Four Count Axis
1
1
1
1
D
1
5
X
X
X
X
are used to program this pattern into the grayscale look-up-
Copyright 2007 Cirrus Logic
1
1
1
0
D
1
4
X
X
X
X
1
1
0
1
D
1
3
X
X
X
X
H O R Z
1
0
0
0
1
1
1
1
0
0
D
1
2
X
X
X
X
0
0
1
0
0
0
1
0
1
1
D
1
1
0
1
0
X
0
1
0
1
0
0
1
0
1
0
D
1
0
0
1
0
X
0
1
0
1
1
0
1
0
0
1
D
9
1
0
0
X
1
0
0
0
D
8
0
0
1
X
Frame 1
0
1
1
1
D
7
1
0
1
X
0
1
1
0
D
6
1
0
0
X
0
1
0
1
D
5
0
1
0
X
0
1
0
0
D
4
0
0
1
X
0
0
0
0
0
1
1
D
3
0
0
1
X
1
1
0
0
0
1
0
D
2
0
0
1
X
0
0
1
0
0
0
1
D
1
0
1
0
X
0
0
1
0
0
0
0
D
0
1
0
0
X
GrySclLUT
Address *4
Frame
00
01
10
11
DS785UM1
Value
Pixel
010
010
010
010