EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 372

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

9
BMSts
9-70
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RxEn:
0x8001_0084 - Read Only
0x0000_0000
0x0000_0000
Bus Master Status Register
RSVD:
TxAct:
TP:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Receive Enable. Writing a one to Receive Enable causes
receive DMA transfers to be enabled. This is reflected in
RxAct (Bus Master Status) being set. This bit is an act-
once-bit and will clear automatically when the enable is
complete. The first time the RxEn bit is set following a
AHB reset, or a RxChRes, the MAC performs a receive
channel initialization. During this initialization the RXDEnq,
and RXStsEnq registers are cleared and the endpoints of
the Receive Descriptor and Status Queues are calculated.
When the initialization is complete, the RxAct (BMSts) is
set.
Reserved. Unknown During Read.
Transmit Active. When this bit is set, the channel is active
and may be in the process of transferring transmit data.
Following a TxDisable Command (Bus Master Control),
when transfers have been halted, this bit is cleared.
Transfer Pending. When the Manual Transfer bit (BMCtl) is
set, the Transfer Pending bit is set, until all internal FIFOs
have either been active for a DMA transfer, or have been
determined to be inactive (that is, empty transmit status
FIFO).
24
8
RSVD
TxAct
23
7
22
6
RSVD
21
5
TP
20
4
RxAct
19
3
18
2
QID
17
1
DS785UM1
16
0