UPD78F0886GA(A)-GAM-AX NEC, UPD78F0886GA(A)-GAM-AX Datasheet - Page 61

• Manufacturer Part Number: UPD78F0886GA(A)-GAM-AX
• Description: 8BIT MCU, 60K FLASH, 3KB RAM, CAN
• Manufacturer: NEC

Specifications of UPD78F0886GA(A)-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm Channels: 6
• Digital Ic Case Style: LQFP
• Core Size: 8bit
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[Instruction format]
[Operation]
[Operand]
[Flag]
[Description]
[Description example]
XOR
• The bit-wise exclusive logical sum is obtained from the destination operand (dst) specified by the 1st operand
• If the exclusive logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is
XOR A, L; The bit-wise exclusive logical sum of the A and L registers is obtained and the result is stored in
Note Except r = A
and the source operand (src) specified by the 2nd operand and the result is stored in the destination operand
(dst).
Logical negation of all bits of the destination operand (dst) is possible by selecting #0FFH for the source
operand (src) with this instruction.
cleared (0).
Mnemonic
Z
×
XOR
the A register.
AC
A, #byte
saddr, #byte
A, r
r, A
A, saddr
dst ← dst ∨ src
XOR dst, src
CY
Operand(dst,src)
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
User's Manual U12326EJ4V0UM
Note
Mnemonic
XOR
Exclusive Logical Sum of Byte Data
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
Operand(dst,src)
Exclusive Or
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