RFHCS362GT-I/SO Microchip Technology, RFHCS362GT-I/SO Datasheet - Page 25

• Manufacturer Part Number: RFHCS362GT-I/SO
• Description: IC CODE HOPPNG ENCDR W/RF 18SOIC
• Manufacturer: Microchip Technology

Specifications of RFHCS362GT-I/SO

• Frequency: 310MHz ~ 440MHz
• Applications: Automotive, Building Access, Garage Openers
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 3.3 kbps
• Power - Output: -12dBm ~ 2dBm
• Current - Transmitting: 11.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

4.5.12
When PWM mode is selected the header length (low
time between preamble and data bits start) can be set
to 10 x T
for compatibility with previous K
els. In Manchester mode, the header length is fixed and
set to 4 x T
4.5.13
RFEN
disabled. If enabled, S3 is only sampled 2 s after the
last button is released and at the start of the first trans-
FIGURE 4-1:
FIGURE 4-2:
MSb
2002 Microchip Technology Inc.
DATA
S2
S0 or S1
QUEUE
RFEN
(2 bits)
selects whether the
E
or 3 x T
E
HEADER
RFEN
.
T
PS
(2 bits)
CRC
E
T
. The 10 x T
PH
1 T
SYNCHRONOUS TRANSMISSION MODE
CODE WORD ORGANIZATION (SYNCHRONOUS TRANSMISSION MODE)
(1-bit)
Vlow
PH
“01,10,11”
RFEN
2
T
E
RFON
S2 S1 S0 S3
Fixed Portion
mode is recommended
EE
output is enabled or
Button
Status
L
OQ
t = 50ms
encoder mod-
35 pulses on S2
Serial Number
Preliminary
(28 bits)
mission. If disabled S3 functions the same as the other
S inputs. For typical implementation of the rfHCS362G/
362F the RFEN bit = 0.
4.6
In Synchronous mode, the code word can be clocked
out on DATA using S2 as a clock. To enter Synchro-
nous mode, S2 must be taken HIGH and then DATA
and S0 or S1 are taken HIGH. After Synchronous mode
is entered, DATA and S2 must be taken LOW. The data
is clocked out on DATA on every falling edge of S2.
Auto-shutoff timer is not disabled in Synchronous
mode. Refer to Figure 4-1 and Figure 4-2.
Preamble
S2 S1 S0 S3
Button
Status
SYNCHRONOUS MODE
rfHCS362G/362F
Header
Encrypted Portion
DISC+ OVR
(12 bits)
69 Data bits
Transmitted
LSb first.
DS41189A-page 25
Sync Counter
(16 bits)
Data
LSb