TEF6607T/V5,518 NXP Semiconductors, TEF6607T/V5,518 Datasheet - Page 9

• Manufacturer Part Number: TEF6607T/V5,518
• Description: IC TUNER CAR RADIO AM/FM 32SOIC
• Manufacturer: NXP Semiconductors

Specifications of TEF6607T/V5,518

• Frequency: *
• Sensitivity: *
• Data Rate - Maximum: *
• Modulation Or Protocol: *
• Applications: *
• Current - Receiving: *
• Data Interface: *
• Memory Size: *
• Antenna Connector: *
• Features: *
• Voltage - Supply: *
• Operating Temperature: *
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935288264518

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
LPC3152_3154
Preliminary data sheet
TFBGA pin name
JTAG
JTAGSEL
TDI
TRST_N
TCK
TMS
TDO
UART
mUART_CTS_N
mUART_RTS_N
UART_RXD
UART_TXD
I
I2C_SDA0
I2C_SCL0
Serial Peripheral Interface (SPI)
SPI_CS_OUT0
SPI_SCK
SPI_MISO
SPI_MOSI
SPI_CS_IN
Digital power supply
VDDI
VDDI_AD
VSSI
VSSI_AD
Peripheral power supply
VDDE_IOA
VDDE_IOB
2
C master/slave interface
[4]
[4]
[4]
Pin description
[4]
[4]
[4]
[4]
[4][6]
[4][6]
TFB
GA
ball
U10
T10
U11
U12
U9
F14
P11
R11
R10
P10
C10
A9
D8
C8
A8
B8
D9
J1;
U13;
A6
M14
H1;
U14;
A7
M15
D1;
M1
L1;
U7
…continued
Digital
I/O
level
[1]
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP1
SUP2
-
-
SUP4
SUP8
All information provided in this document is subject to legal disclaimers.
Application
function
DI / GPIO
DI / GPIO
DI / GPIO
DI / GPIO
DI / GPIO
DO
DI / GPIO
DO / GPIO
DI / GPIO
DO / GPIO
DIO
DIO
DO
DIO
DIO
DIO
DI
Supply
Supply
Ground
Ground
Supply
Supply
Rev. 0.12 — 27 May 2010
Table 11
Pin
state
after
reset
I:PD
I:PU
I:PD
I:PD
I:PU
Z
I
O
I
O
I
I
O
I
I
I
I
for pin function selection of multiplexed pins.
[2]
Cell type
[3]
DIO1
DIO1
DIO1
DIO1
DIO1
DIO2
DIO1
DIO1
DIO1
DIO1
IICD
IICC
DIO4
DIO4
DIO4
DIO4
DIO4
CS2
CS2
CG2
CG2
PS1
PS1
Description
JTAG selection. Controls which digital die
TAP controller is configured in the JTAG chain
along with the analog die TAP controller. Must
be LOW during power-on reset.
JTAG data Input
JTAG TAP Controller Reset Input. Must be
LOW during power-on reset.
JTAG clock input
JTAG mode select input
JTAG data output
UART Clear-To-Send (CTS) (active LOW)
UART Ready-To-Send (RTS) (active LOW)
UART serial input
UART serial output
I
I
SPI chip select output (master)
SPI clock input (slave) / clock output (master)
SPI data input (master) / data output (slave)
SPI data output (master) / data input (slave)
SPI chip select input (slave)
Digital core supply
Core supply for digital logic on analog die -
has to be connected to 1.4/1.8 V rail
Digital core ground
Digital core ground of analog die
Peripheral supply NAND flash controller
Peripheral supply LCD interface / SDRAM
interface
2
2
C-bus data line
C-bus clock line
LPC3152/3154
© NXP B.V. 2010. All rights reserved.
9 of 88