TEF6607T/V5,518 NXP Semiconductors, TEF6607T/V5,518 Datasheet - Page 17

• Manufacturer Part Number: TEF6607T/V5,518
• Description: IC TUNER CAR RADIO AM/FM 32SOIC
• Manufacturer: NXP Semiconductors

Specifications of TEF6607T/V5,518

• Frequency: *
• Sensitivity: *
• Data Rate - Maximum: *
• Modulation Or Protocol: *
• Applications: *
• Current - Receiving: *
• Data Interface: *
• Memory Size: *
• Antenna Connector: *
• Features: *
• Voltage - Supply: *
• Operating Temperature: *
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935288264518

NXP Semiconductors
LPC3152_3154
Preliminary data sheet
6.3 JTAG
6.4 NAND flash controller
Table 7.
The JTAG interface allows the incorporation of the LPC3152/3154 in a JTAG scan chain.
This module has the following features:
The NAND flash controller is used as a dedicated interface to NAND flash devices.
Figure 4
module is formed by a controller block that controls the flow of data from/to the AHB bus
through the NAND flash controller block to/from the (external) NAND flash. An error
correction encoder/decoder module allows for hardware error correction for support of
Multi-Level Cell (MLC) NAND flash devices. In the LPC3154, the NAND flash controller is
connected to the AES block to support secure (encrypted) code execution (see
Section
Before data is written from the buffer to the NAND flash, optionally it is first protected by
an error correction code generated by the ECC module. After data is read from the NAND
flash, the error correction module corrects errors, and/or the AES decryption module can
decrypt data.
Block
PSU/Li-ion charger
Audio codec
RTC
•
•
•
ARM926 debug access
Boundary scan
The ARM926 debug access can be permanently disabled through the JTAG security
bits in the One-Time Programmable memory (OTP) block.
6.21).
shows a block diagram of the NAND flash controller module. The heart of the
Analog die register addresses (I
All information provided in this document is subject to legal disclaimers.
Rev. 0.12 — 27 May 2010
2
C1 slave device address 0x0C)
Address offset
0x0000 - 0x000F
0x0010 - 0x001F
0x0020 - 0x002F
LPC3152/3154
© NXP B.V. 2010. All rights reserved.
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