AD9874ABST Analog Devices Inc, AD9874ABST Datasheet
AD9874ABST
Specifications of AD9874ABST
Available stocks
Related parts for AD9874ABST
AD9874ABST Summary of contents
Page 1
FEATURES 10 MHz to 300 MHz Input Frequency 7.2 kHz to 270 kHz Output Signal Bandwidth 8.1 dB SSB NF 0 dBm IIP3 AGC Free Range up to –34 dBm 12 dB Continuous AGC Range 16 dB Front End Attenuator ...
Page 2
AD9874 TABLE OF CONTENTS AD9874—SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . ...
Page 3
AD9874–SPECIFICATIONS VDDQ = VDDP = 2 5 MSPS, f CLK Parameter SYSTEM DYNAMIC PERFORMANCE SSB Noise Figure @ Min VGA Attenuation Max VGA Attenuation 3, 4 Dynamic Range with AGC Enabled ...
Page 4
AD9874 DIGITAL SPECIFICATIONS MSPS 109.65 MHz 107.4 MHz, f CLK IF LO Parameter DECIMATOR 2 Decimation Factor Pass-Band Width Pass-Band Gain Variation Alias Attenuation SPI-READ OPERATION (See Figure 1a) PC Clock Frequency PC ...
Page 5
... JA = 17°C/W JC Model Temperature Range AD9874ABST –40°C to +85°C AD9874EB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
Page 6
AD9874 Pin Mnemonic Description 1 MXOP Mixer Output, Positive. 2 MXON Mixer Output, Negative. 3 GNDF Ground for Front End of ADC. 4 IF2N Second IF Input (to ADC), Negative. 5 IF2P Second IF Input (to ADC), Positive. 6 VDDF ...
Page 7
DEFINITION OF SPECIFICATIONS/TEST METHODS Single-Sideband Noise Figure (SSB NF) Noise figure (NF) is defined as the degradation in SNR perfor- mance (in dB input signal after it passes through a component or system. It can be expressed ...
Page 8
AD9874–Typical Performance Characteristics (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data ...
Page 9
VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and ...
Page 10
AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC ...
Page 11
VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and ...
Page 12
AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5 –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC ...
Page 13
SERIAL PERIPHERAL INTERFACE (SPI) The serial peripheral interface (SPI bidirectional serial port used to load configuration information into the registers listed below as well as to read back their contents. Table I provides a list of ...
Page 14
AD9874 Address Bit (Hex) Breakdown Width Default Value CLOCK SYNTHESIZER 0x10 (5: 0x11 (7:0) 8 0x38 0x12 (4:0) 5 0x00 0x13 (7:0) 8 0x3C 0x14 ( ( (4: (1: 0x15 ...
Page 15
SERIAL PORT INTERFACE (SPI) The serial port of the AD9874 has 3-wire or 4-wire SPI capability, allowing read/write access to all registers that configure the device’s internal parameters. The default 3-wire serial commu- nication port consists of a clock (PC), ...
Page 16
AD9874 SYNCHRONOUS SERIAL INTERFACE (SSI) The AD9874 provides a high degree of programmability of its SSI output data format, control signals, and timing parameters to accommodate various digital interfaces 3-wire digital interface, the AD9874 provides a frame sync ...
Page 17
CLKOUT FS DOUT SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS ...
Page 18
AD9874 The AD9874 also provides the means for controlling the switching characteristics of the digital output signals via the DS (drive strength) field of the SSICRB. This feature is useful in limiting switching transients and noise from the digital out- ...
Page 19
AD9874 PC SCK SPI PE SEL PD MOSI DOUTB MISO CLKOUT RSCLK SSI FS RFS DOUTA DR Figure 4b. Example of AD9874 and ADSP-2153x Interface As shown in Figure 4b, AD9874’s synchronous serial interface (SSI) links the receive data stream ...
Page 20
AD9874 An example may help illustrate how the values of LOA, LOB, and LOR can be selected. Consider an application employing a 13 MHz crystal oscillator (i.e., f REF requirement that f = 100 kHz and f REF high side ...
Page 21
CLOCK SYNTHESIZER The clock synthesizer is a fully programmable integer-N PLL capable of 2.2 kHz resolution at clock input frequencies MHz and reference frequencies MHz similar to the LO synthesizer described in ...
Page 22
AD9874 0 –10 –20 –30 –40 –50 –60 –70 – – –100 –110 –120 –130 –140 –25 –20 –15 –10 –5 0 FREQUENCY OFFSET – kHz Figure 7c. CLK Phase Noise vs. Charge Pump ...
Page 23
The mixer’s differential LO port is driven by the LO buffer stage shown in Figure 6, which can be driven single-ended or differential. Since it is self-biasing, the LO signal level can be ac-coupled and range from 0.3 V p-p ...
Page 24
AD9874 Based on these characterization curves, a LNA/mixer bias setting of 3_3 is suitable for most applications since it will provide the greatest dynamic range in the presence of multiple unfiltered interferers. However, portable radio applications demanding the lowest possible ...
Page 25
The signal transfer function of the AD9874 possesses inherent antialias filtering by virtue of the continuous-time portions of the loop filter in the band-pass - modulator. Figure 13b illustrates this property by plotting the nominal signal transfer function of the ...
Page 26
AD9874 Once the AD9874 has been tuned, the noise figure degradation attributed solely to the temperature drift of the LC and RC resonators is minimal. Since the drift of the RC resonator is actually negligible compared to that of the ...
Page 27
Figures 16a and 16b show expanded views of the pass band for the two possible configurations of the third decimation filter. When decimating by 60n (K = 0), the pass-band gain variation is 1.2 dB; when decimating by 48n (K ...
Page 28
AD9874 - ADC DEC1 12 FS VGA DAC GCP C DAC Figure 18. Functional Block Diagram of VGA and AGC VARIABLE GAIN AMPLIFIER OPERATION WITH AUTOMATIC GAIN CONTROL The AD9874 contains both a variable gain amplifier (VGA) and a digital ...
Page 29
Referring to Figure 18, the gain of the VGA is set by an 8-bit con- trol DAC that provides a control signal to the VGA appearing at the gain control pin (GCP). For applications implementing auto- matic gain control, the ...
Page 30
AD9874 the maximum bandwidth is 9 kHz. A general expression for the attack bandwidth is: × × MHz 2 A CLK and the corresponding attack time is: ( AGCA 2 = ...
Page 31
Table XII indicates which AGCA values are reasonable for various decimation factors. The white cells indicate that the (decimation factor/AGCA) combination works well; the light gray cells indicate ringing and an increase in the AGC settling time; and the dark ...
Page 32
AD9874 Figure 22b plots the nominal system NF with 16-bit output data as a function of AGC in both narrow-band and wideband mode. In wideband mode, the NF curve is virtually unchanged relative to the 24-bit output data because the ...
Page 33
Figure 23b. Same as Figure 23a Excluding LO Frequencies Known to Produce Large In-Band Spurs Figure 23b shows that omitting the LO frequencies given by Equation 12 for and ...
Page 34
AD9874 EXTERNAL PASSIVE COMPONENT REQUIREMENTS Figure 26 shows an example circuit using the AD9874 and Table XIV shows the nominal dc bias voltages seen at the differ- ent pins. The purpose is to show the various external passive components required ...
Page 35
PRESELECT RF TUNER FILTER INPUT LNA VCO ADF42xx PLL SYN REFIN CRYSTAL OSCILLATOR Figure 27. Typical Dual Conversion Superheterodyne Application Using the AD9874 This second IF signal is then digitized by the - ADC, demodu- lated into its quadrature I ...
Page 36
AD9874 and digital driver strength should be set to their lowest pos- sible settings to minimize the potential harmful effects of digital induced noise while preserving a reliable data link to the DSP. Note that the SSICRA, SSICRB, and SSIORD ...
Page 37
DUPLEXER PRESELECT X LNA MIXER GAIN = –2dB GAIN = 22dB GAIN = –3dB NF = 2dB NF = 1dB NF = 3dB Figure 29. Example of Split Path Rx Architecture to Increase Receiver Dynamic Range Capabilities Split Path Rx ...
Page 38
AD9874 results adjustment of the clip point, allowing the clip point difference to be calibrated to exactly 24 dB, so that a simple 5-bit shift would make up the gain difference. The attenuated path can handle ...
Page 39
SEATING 0.05 PLANE ROTATED 90 CCW REV. A OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 1.60 MAX PIN 1 INDICATOR 0.75 0.60 0.45 SEATING PLANE 0.20 0.09 VIEW A ...
Page 40
AD9874 Revision History Location 3/03—Data sheet changed from REV REV. A Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . ...