EM250-BBRD-R Ember, EM250-BBRD-R Datasheet - Page 66

• Manufacturer Part Number: EM250-BBRD-R
• Description: EM250 BREAKOUT BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4r

Specifications of EM250-BBRD-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1024

EM250
120-0082-000S
To generate interrupts to the CPU, the interrupt masks in the
abled.
5.3.2
The SC2 I
3. The I
not implemented, so multiple master applications are not supported. The I
signals, and external pull-up resistors are required.
The SC2 I
The following signals can be made available on the GPIO pins:
The I
by a clock division ratio from the 24MHz clock:
EXP is written to the
tings for Standard I
Note that, at 400kbps, the I
I
The I
SC_I2CSTART
summarizes these frames.
Full I
essary segment transitions are shown in Figure 7. ACK or NACK generation of an I
determined with the register bit
Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the transmitted
character contain the 7-bit address. The remaining lower bit contains the command type (“read” or “write”).
Generation of a 10-bit address is accomplished with two transmit segments. The upper 5 bits of the first
transmit character must be set to
dress. The remaining lower bit contains the command type (“read” or “write”). The second transmit segment
is for the remaining 8 bits of the 10-bit address.
2
C compliant, the rate needs to be lowered to 375kbps.
Transmitted character while transmit FIFO was empty (Transmit underrun error)
Programmable clock frequency (400kHz max.)
7- and 10-bit addressing
SDA (serial data)
SCL (serial clock)
Nominal Rate = 24MHz / ( 2 * (LIN + 1) * 2
2
2
2
C frames have to be constructed under software control by generating individual I
C Master controller obtains its reference clock from a programmable clock generator. Clock rates are set
C Master controller supports generation of various frame segments defined by the register bits
2
I
C Master controller supports Standard (100kbps) and Fast (400kbps) I
2
2
2
C Master Mode
C controller is only available in master mode. The SC2 I
C mode has the following features:
Nominal Rate
,
100kbps
375kbps
400kbps
SC_I2CSTOP
2
C (100kbps) and Fast I
SC2_RATEEXP
2
,
C specification requires the minimum low period of SCL to be 1.3µs. To be strictly
SC_I2CSEND
SC_I2CACK
Table 26. I
0x1E
register and LIN to the
. The next 2 bits are for the 2 most significant bits of the 10-bit ad-
2
, and
C (400kbps) operation.
2
in the
Page 66
C Nominal Rate Programming
EXP
SC2_RATELIN
SC_I2CRECV
)
SC2_I2CCTRL2
14
15
14
SC2_RATELIN
within the
INT_SC2CFG
2
C controller is enabled with
register.
SC2_I2CCTRL1
register. Table 26 shows the rate set-
2
and
C signals are pure open-collector
2
C modes. Address arbitration is
INT_CFG
2
C receive frame segment is
SC2_RATEEXP
register. Table 27
2
C segments. All nec-
register must be en-
3
1
1
SC2_MODE
set to