EM250-BBRD-R Ember, EM250-BBRD-R Datasheet - Page 47

• Manufacturer Part Number: EM250-BBRD-R
• Description: EM250 BREAKOUT BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4r

Specifications of EM250-BBRD-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1024

Full I
essary segment transitions are shown in Figure 7. ACK or NACK generation of an I
determined with the register bit
Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the transmitted
character contain the 7-bit address. The remaining lower bit contains the command type (“read” or “write”).
Generation of a 10-bit address is accomplished with two transmit segments. The upper 5 bits of the first
transmit character must be set to
dress. The remaining lower bit contains the command type (“read” or “write”). The second transmit segment
is for the remaining 8 bits of the 10-bit address.
Characters received and transmitted are passed through receive and transmit FIFOs. The SC1 I
transmit and receive FIFOs are 1-byte deep. These FIFOs are accessed under software control.
(Re)start and stop segments are initiated by setting the register bits
SC1_I2CCTRL1
SC_I2CCMDFIN
To initiate a transmit segment, the data have to be written to the
the register bit
tively, the register bit
A receive segment is initiated by setting the register bit
until it clears, and then reading from the
in the
indicates if a NACK or ACK was received from an I
Interrupts are generated on the following events:
Bus command (
Character transmitted and slave device responded with NACK
2
C frames have to be constructed under software control by generating individual I
SC1_I2CSTAT
register followed by waiting until they have cleared. Alternatively, the register bit
in the
SC_I2CSEND
SC_I2CSTART/SC_I2CSTOP
can be used for waiting. Now the register bit
SC1_I2CSTAT
SC_I2CTXFIN
RECEIVE Segment
STOP Segment
with NACK
in the
SC_I2CACK
0x1E
SC1_I2CCTRL1
can be used for waiting.
in the
Figure 7. I
. The next 2 bits are for the 2 most significant bits of the 10-bit ad-
SC1_DATA
Page 47
SC1_I2CSTAT
in the
START Segment
) completed (0 to 1 transition of
2
C Segment Transitions
2
C slave device.
register, and completed by waiting until it clears. Alterna-
SC1_I2CCTRL2
IDLE
data register. Alternatively, the register bit
SC_I2CRECV
can be used for waiting.
NO
TRANSMIT Segment
RECEIVE Segment
SC_I2CRXNAK
SC1_DATA
register.
received ACK ?
SC_I2CSTART
in the
with ACK
SC1_I2CCTRL1
YES
data register, followed by setting
SC_I2CCMDFIN
2
in the
C receive frame segment is
or
SC_I2CSTOP
SC1_I2CSTAT
2
C segments. All nec-
register, waiting
2
C master
)
SC_I2CRXFIN
EM250
120-0082-000S
in the
register