EM250-BBRD-R Ember, EM250-BBRD-R Datasheet - Page 64

• Manufacturer Part Number: EM250-BBRD-R
• Description: EM250 BREAKOUT BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4r

Specifications of EM250-BBRD-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1024

EM250
120-0082-000S
2
2
2
2
2
2
2
0
0
0
0
0
0
0
SC2_SPICFG
0
0
0
0
1
-
-
When the slave select (nSSEL) signal is asserted (by the Master), SC2 SPI transmit data is driven to the output
pin MISO and SC2 SPI data is received from the input pin MOSI. When the slave select (nSSEL) signal is deas-
serted (by the Master), no data is transferred on the MISO or MOSI pins and the output pin MISO is tri-stated.
The slave select signal nSSEL is used to enable driving the serialized data output signal MISO. It is also used to
reset the SC2 SPI slave shift register.
Characters received and transmitted are passed through receive and transmit FIFOs. The transmit and receive
FIFOs are 4 bytes deep. These FIFOs are accessed under software control by accessing the
ister or under hardware control using a DMA controller.
Any character received is stored in the (empty) receive FIFO. The register bit
SC2_SPISTAT
software or DMA is not reading from the receive FIFO, the receive FIFO will store up to 4 characters. Any fur-
ther reception is dropped, and the register bit
hardware generates the
til the RX FIFO is drained. Once the DMA marks a RX error, there are two conditions that will clear the error
indication: setting the appropriate
priate DMA buffer after it has unloaded.
0
0
1
1
-
-
-
0
1
0
1
-
-
-
SC2-4S
mode
SC2-4S
mode
SC2-4S
mode
SC2-4S
mode
SC2-4S
mode
SC2-3M
mode
SC2-2 mode
register is set to indicate that not all received characters are read out from receive FIFO. If
INT_SCRXOVF
Table 25. SC2 SPI Slave Formats
MSCLK
MSCLK
MSCLK
MSCLK
Frame Format
Same as above except LSB first instead of MSB first
Illegal
Illegal
MISO
MISO
MISO
MISO
nSSEL
MOSI
nSSEL
MOSI
nSSEL
MOSI
nSSEL
MOSI
out
out
out
out
SC_TX/RXDMARST
in
in
in
in
in
in
in
in
interrupt, but the DMA register will not indicate the error condition un-
Page 64
RX[7]
TX[7]
RX[7]
TX[7]
RX[7]
TX[7]
RX[7]
TX[7]
SC_SPIRXOVF
bit in the
RX[6]
TX[6]
RX[6]
TX[6]
RX[6]
TX[6]
RX[6]
TX[6]
RX[5]
RX[5]
RX[5]
RX[5]
TX[5]
TX[5]
TX[5]
TX[5]
in the
SC2_DMACTRL
RX[4]
TX[4]
RX[4]
TX[4]
RX[4]
TX[4]
RX[4]
TX[4]
SC2_SPISTAT
RX[3]
RX[3]
RX[3]
RX[3]
TX[3]
TX[3]
TX[3]
TX[3]
register, or loading the appro-
SC_SPIRXVAL
RX[2]
RX[2]
RX[2]
RX[2]
TX[2]
TX[2]
TX[2]
TX[2]
register is set. The RX FIFO
RX[1]
TX[1]
RX[1]
TX[1]
RX[1]
TX[1]
RX[1]
TX[1]
SC2_DATA
in the
RX[0]
RX[0]
RX[0]
RX[0]
TX[0]
TX[0]
TX[0]
TX[0]
data reg-