M37544G2AGP Renesas Electronics America, M37544G2AGP Datasheet - Page 32

• Manufacturer Part Number: M37544G2AGP
• Description: MCU 2/5V 8K 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.1.04
REJ03B0012-0104Z
Fig. 32 Structure of serial I/O-related registers
7544 Group
b7
b7
2004.06.08
b0
b0
Serial I/O status register
(SIOSTS : address 0019
UART control register
(UARTCON : address 001B
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Disable (returns “1” when read)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P1
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Disable (return “1” when read)
1
/T
X
page 30 of 66
D
1
P-channel output disable bit (POFF)
16
, initial value: 00
16
, initial value: E0
16
)
16
)
b7
b0
Serial I/O control register
(SIOCON : address 001A
BRG count source selection bit (CSS)
0: f(X
1: f(X
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
1: External clock input when clock synchronous serial
S
0: P1
1: P1
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
1: Serial I/O enabled
RDY
(pins P1
(pins P1
serial I/O is selected, BRG output divided by 16
when UART is selected.
I/O is selected, external clock input divided by 16
when UART is selected.
IN
IN
3
3
output enable bit (SRDY)
pin operates as ordinary I/O pin
pin operates as S
)
)/4
0
0
to P1
to P1
3
3
operate as ordinary I/O pins)
operate as serial I/O pins)
16
RDY
, initial value: 00
output pin
16
)