M37544G2AGP Renesas Electronics America, M37544G2AGP Datasheet - Page 24

• Manufacturer Part Number: M37544G2AGP
• Description: MCU 2/5V 8K 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.1.04
REJ03B0012-0104Z
7544 Group
Timers
The 7544 Group has 3 timers: timer 1, timer A and timer X.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to “1”.
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
“1”.
Prescaler 1 is an 8-bit prescaler and counts the signal selected by
the timer 1 count source selection bit.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows. The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is writ-
ten to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex-
ecuted, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal selected by the timer 1 count source
selection bit. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach “00
the prescaler 1 latch is reloaded into Prescaler 1 and count contin-
ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the under-
flow signal of Prescaler 1 is input. When the contents of Timer 1
reach “00
timer 1 latch is reloaded into Timer 1 and count continues. The di-
vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1) (m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Timer 1 cannot stop counting by software.
Timer 1
16
”, an underflow occurs at the next count clock, and the
16
2004.06.08
”, an underflow occurs at the next count clock, and
page 22 of 66
Timer A is a 16-bit timer and counts the signal selected by the
timer A count source selection bit. When Timer A underflows, the
timer A interrupt request bit is set to “1”.
Timer A consists of the low-order of Timer A (TAL) and the high-or-
der of Timer A (TAH).
Timer A has the timer A latch to retain the reload value. The value
of timer A latch is set to Timer A at the timing shown below.
• When Timer A undeflows.
• When an active edge is input from CNTR
period measurement mode and pulse width HL continuously mea-
surement mode).
When writing to both the low-order of Timer A (TAL) and the high-
order of Timer A (TAH) is executed, the value is written to both the
timer A latch and Timer A.
When reading from the low-order of Timer A (TAL) and the high-or-
der of Timer A (TAH) is executed, the following values are read out
according to the operating mode.
• In timer mode, event counter mode:
The count value of Timer A is read out.
• In period measurement mode, pulse width HL continuously mea-
surement mode:
The measured value is read out.
Be sure to write to/read out the low-order of Timer A (TAL) and the
high-order of Timer A (TAH) in the following order;
Read
Read the high-order of Timer A (TAH) first, and the low-order of
Timer A (TAL) next and be sure to read out both TAH and TAL.
Write
Write to the low-order of Timer A (TAL) first, and the high-order of
Timer A (TAH) next and be sure to write to both TAL and TAH.
Timer A can be selected in one of 4 operating modes by setting
the timer A mode register.
(1) Timer mode
Timer A counts the selected by the timer A count source selection
bit. Each time the count clock is input, the contents of Timer A is
decremented by 1. When the contents of Timer A reach “0000
an underflow occurs at the next count clock, and the timer A latch
is reloaded into Timer A. The division ratio of Timer A is 1/(n+1)
provided that the value of Timer A is n.
(2) Period measurement mode
In the period measurement mode, the pulse period input from the
P0
CNTR
CNTR
latch is reloaded in Timer A and count continues. The active edge
of CNTR
the CNTR
input from CNTR
once.
Timer A
0
/CNTR
1
1
pin input signal. Simultaneously, the value in the timer A
interrupt request is generated at rising/falling edge of
1
1
pin input signal can be selected from rising or falling by
1
active edge switch bit .The count value when trigger
pin is measured.
1
pin is accepted is retained until Timer A is read
1
pin (valid only when
16
”,