M37544G2AGP Renesas Electronics America, M37544G2AGP Datasheet - Page 29

• Manufacturer Part Number: M37544G2AGP
• Description: MCU 2/5V 8K 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.1.04
REJ03B0012-0104Z
7544 Group
Serial I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Fig. 28 Block diagram of clock synchronous serial I/O
Fig. 29 Operation of clock synchronous serial I/O function
Serial I/O
Write pulse to receive/transmit
buffer register (address 0018
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Receive enable signal S
P1
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
P1
2004.06.08
P1
P1
3
2
0
/S
1
/S
/R
/T
RDY
CLK
X
X
X
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
D
IN
D
Serial output TxD
Serial input RxD
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
data is output continuously from the TxD pin.
BRG count source selection bit
page 27 of 66
RDY
F/F
16
)
TBE = 0
1/4
Falling-edge detector
TBE = 1
TSC = 0
Receive buffer register
D
D
Receive shift register
0
0
Transmit buffer register
Transmit shift register
Data bus
Data bus
D
D
1
1
Address 0018
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 0018
Shift clock
Address 001C
D
D
2
2
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit 6)
to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
16
Clock control circuit
16
D
D
Clock control circuit
16
3
3
Serial I/O control register
Transmit interrupt source selection bit
Receive buffer full flag (RBF)
1/4
Serial I/O status register
D
D
4
4
Receive interrupt request (RI)
D
D
5
5
Transmit buffer empty flag (TBE)
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
D
D
6
6
Address 001A
Address 0019
Overrun error (OE)
detection
RBF = 1
TSC = 1
D
D
7
7
16
16