M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 85

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The operation procedure in CPU reprogramming mode is de-
scribed below.
Note: The following are necessary other than this:
Fig. 80 Flash command register bit configuration
82
< Beginning procedure >
Apply 0 V to the CNVss/V
After CPU reprogramming mode control program is transferred to
Set “1" to the CPU reprogramming mode select bit.
Apply V
Wait till CNV
The operation of the flash memory is executed by software-com-
mand-writing to the flash command register .
CPU reprogramming mode operation procedure
whether the CPU reprogramming mode is valid.
Read the CPU reprogramming mode monitor flag to confirm
internal RAM, jump to this control program on RAM. (The follow-
ing operations are controlled by this control program).
Note: The flash command register is write-only register.
7
•Control for data which is input from the external (serial I/O
•Initial setting for ports etc.
•Writing to the watchdog timer
etc.) and to be programmed to the flash memory
6
PP
H to the CNV
5
SS
4
/V
<Software command name>
• Read command
• Program command
• Program verify command
• Erase command
• Erase verify command
• Reset command
PP
3
pin becomes 12 V.
2
SS
1
PP
/V
PP
0
pin for reset release.
pin.
Writing of software command
Flash command register
(FCMD : address 0FFF
<Command code>
“00
“40
“C0
“20
“A0
“FF
16
16
16
16
16
16
”
”
” + “20
”
” + “FF
”
16
)
16
16
”
”
Fig. 81 CPU mode register bit configuration in CPU rewriting
When “00
M38869FFAHP/GP enters the read mode. The contents of the
corresponding address can be read by reading the flash memory
(For instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
< Release procedure >
Each software command is explained as follows.
Apply 0V to the CNV
Wait till CNV
Set the CPU reprogramming mode select bit to “0.”
Read command
b 7
mode
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
" is written to the flash command register, the
SS
/V
PP
MITSUBISHI MICROCOMPUTERS
SS
pin becomes 0V.
/V
0
PP
pin.
b 0
0
C P U m o d e r e g i s t e r
(
C P U M : a d d r e s s
P r o c e s s o r m o d e b i t s
S t a c k p a g e s e l e c t i o n b i t
R e s e r v e d
( D o n o t w r i t e “ 0 ” t o t h i s b i t w h e n u s i n g
P o r t X
M a i n c l o c k ( X
M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s
X
b 1 b 0
b 7 b 6
0
0
1
0 : 0 p a g e
1 : 1 p a g e
C I N
0
0
1
1
0 : I / O p o r t f u n c t i o n ( s t o p o s c i l l a t i n g )
1 : X
0 : O s c i l l a t i n g
1 : S t o p p e d
– X
X : N o t a v a i l a b l e
3886 Group
0 : S i n g l e - c h i p m o d e
1 : N o t a v a i l a b l e
C
0 :
1 :
0 :
1 : N o t a v a i l a b l e
C I N
s w i t c h b i t
C O U T
– X
= f ( X
= f ( X
= f ( X
C O U T
0 0 3 B
I N
o s c i l l a t i o n f u n c t i o n . )
– X
I N
I N
C I N
O U T
) / 2 ( h i g h - s p e e d m o d e )
) / 8 ( m i d d l e - s p e e d m o d e )
o s c i l l a t i n g f u n c t i o n
) / 2 ( l o w - s p e e d m o d e )
1 6
) s t o p b i t
)