M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 50

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

[I
(S2D)] 0017
The I
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
S
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(X
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 13.
Do not set “00000
tion set bit (SSC4 to SSC0).
Refer to Table 14, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: S
An interrupt can occur when detecting the falling or rising edge of
the S
pin interrupt pin.
•Bit 6: S
This bit selects the pin of which interrupt becomes valid between
the S
Note: When changing the setting of the S
•Bit 7: START/STOP condition generating selection bit
Setup/Hold time when the START/STOP condition is generated
can be selected.
Cycle number of system clock becomes standard for setup/hold
time. Additionally, setup/hold time is different between the START
condition and the STP condition. (Refer to Tables 11 and 12.) Set
“1” to this bit when the system clock frequency is 4 MHz or more.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
CL
2
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I
(address 0013
parison of the RBW bit of the I
0013
when the 7-bit addressing format is selected, refer to Figure 46,
(1) and (2).
7-bit addressing format
C START/STOP Condition Control Register
release time, setup time, and hold time change the detection
2
CL
CL
lection bit, the S
interface enable bit ES0, the S
set. When selecting the S
rupt before the S
S
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
C START/STOP condition control register (address 0017
DA
2
16
pin and the S
C control register (address 0015
or S
CL
CL
(STSPSEL)
interrupt pin selection bit, or the I
) is not performed. For the data transmission format
/S
/S
DA
DA
DA
pin. This bit selects the polarity of the S
interrupt pin polarity selection bit (SIP)
interrupt pin selection bit (SIS)
16
16
2
” or an odd number to the START/STOP condi-
). At the time of this comparison, address com-
CL
CL
DA
/S
/S
pin.
DA
DA
interrupt pin selection bit, or the I
interrupt pin polarity selection bit, the S
IN
CL
) because these time are measured
/S
DA
CL
2
interrupt source, disable the inter-
/S
C address register (address
CL
DA
/S
2
interrupt request bit may be
C-BUS interface enable bit
DA
16
) to “0.” The first 7-bit
interrupt pin polarity se-
2
C address register
CL
2
or S
C-BUS
16
DA
CL
)
/
10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I
comparison, an address comparison between the RBW bit of
the I
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RBW bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I
“1.” After the second-byte address data is stored into the I
data shift register (address 0012
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RBW bit of the I
(address 0013
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the I
mission format when the 10-bit addressing format is selected,
refer to Figure 46, (3) and (4).
2
2
2
C address register (address 0013
C control register (address 0015
C address register (address 0013
2
C address register (address 0013
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
16
) to “1” by software. This processing can make
MITSUBISHI MICROCOMPUTERS
2
C status register (address 0014
16
), perform an address com-
3886 Group
16
16
16
). For the data trans-
16
) to “1.” An address
2
). At the time of this
C address register
) and the R/W bit
16
) is set to
2
47
C