M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 23

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 6 Interrupt vector addresses and priority
Notes 1: Vector addresses contain interrupt jump destination addresses.
20
INT
INT
Output buffer
empty (OBE)
Serial I/O1
transmission
S
Timer X
Timer Y
Timer 1
Timer 2
S
CNTR
Serial I/O2
INT
I
INT
Key-on wake-up
BRK instruction
Reset (Note 2)
Input buffer full
(IBF)
Serial I/O1
reception
CNTR
Key-on wake-up
I
INT
A-D converter
Interrupt Source
2
2
CL
CL
C
C
1
0
2
4
, S
, S
3
2: Reset function in the same way as an interrupt with the highest priority.
1
0
DA
DA
Priority
10
12
13
14
15
16
17
11
1
2
3
4
5
6
7
8
9
Vector Addresses (Note 1)
FFDD
FFFD
FFFB
FFEF
FFED
FFEB
FFDF
FFF9
FFF7
FFF5
FFF3
FFF1
FFE9
FFE7
FFE5
FFE3
FFE1
High
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
FFEC
FFDE
FFDC
FFFC
FFFA
FFEE
FFEA
FFE8
FFE6
FFE4
FFE2
FFE0
FFF8
FFF6
FFF4
FFF2
FFF0
Low
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At detection of either rising or
falling edge of CNTR
At reset
At input data bus buffer writing
At detection of either rising or
falling edge of INT
At output data bus buffer read-
ing
At detection of either rising or
falling edge of S
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of S
At detection of either rising or
falling edge of CNTR
At falling of port P3 (at input) in-
put logical level AND
At completion of serial I/O2 data
transfer
At completion of data transfer
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At completion of A-D conversion
At BRK instruction execution
At detection of either rising or
falling edge of INT
At completion of data transfer
At detection of either rising or
falling edge of INT
At falling of port P3 (at input) in-
put logical level AND
Generating Conditions
Interrupt Request
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CL
CL
1
3
4
0
2
or S
or S
input
input
input
input
input
0
1
input
input
DA
DA
MITSUBISHI MICROCOMPUTERS
External interrupt
(active edge selectable)
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
STP release timer underflow
External interrupt (falling valid)
3886 Group
Remarks