M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 80

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Input command code 40
the low-order 8 bits and the high-order 8 bits of the address and
then program data. Programming is initiated at the last rising edge
of the serial clock during program data transfer. The BUSY pin is
driven high during program operation. Programming is completed
within 10 s as measured by the internal timer, and the BUSY pin
is pulled low.
Fig. 74 Timings during programming
Input command code C0
the OE pin low. When this is done, The M38869FFAHP/GP verify-
reads the programmed address’s contents, and then latchs it into
Fig. 75 Timings during program verify
Program command
Program verify command
__
SCLK
SDA
OE
BUSY
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
Command code input (40
in the floating state during the period of th
0 0 0 0 0 0 1 0
16
16
in the first transfer. Proceed and input
in the first transfer. Proceed and drive
SCLK
SDA
OE
BUSY
16
“L”
) Program address input (L) Program address input (H)
t
CH
Command code input (C0
A
0
0 0 0 0 0 0 1 1
(C-E)
after the last rising edge of SCLK (at the 8th bit).
A
7
16
t
CH
)
t
CRPV
A
8
Verify read
Note : A programming operation is not completed by executing the
the internal data latch. When the OE pin is released back high and
serial clock is input to the SCLK pin, the verify data that has been
latched into the data latch is serially output from the SDA pin.
t
WR
program command once. Always be sure to execute a pro-
gram verify command after executing the program command.
When the failure is found in the verification, the user must re-
peatedly execute the program command until the pass in the
verification. Refer to Figure 71 for the programming flowchart.
t
RC
A
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
15
t
CH
D
Verify data output
0
Program data input
D
0
MITSUBISHI MICROCOMPUTERS
D
7
__
D
7
Program
t
WP
3886 Group
t
PC
77