M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 73

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The erase command is executed by inputting command code 20
in the first cycle and command code 20
cycle. The command code is latched into the internal command
latch at the rising edges of the WE input in the first cycle and in
the second cycle, respectively. The erase operation is initiated at
the rising edge of the WE input in the second cycle, and the
memory contents are collectively erased within 9.5 ms as mea-
sured by the internal timer. Note that data 00
all memory locations before executing the erase command.
Note: An erase operation is not completed by executing the erase
Fig. 70 Input/output timings during erasing (verify data is output at the same timing as for read.)
70
Erase command
Address
CE
OE
WE
Data
V
PP
command once. Always be sure to execute an erase verify
command after executing the erase command. When the fail-
ure is found in this verification, the user must repeatedly ex-
ecute the erase command until the pass. Refer to Figure 71
for the erase flowchart.
V
V
PP
PP
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
H
L
___
t
VSC
t
CS
___
t
t
WC
RRW
t
WP
t
DS
20
16
t
t
DH
CH
16
again in the second
t
16
WPH
must be written to
t
CS
t
WP
t
DS
20
16
t
t
DH
CH
16
Erase
t
DE
The user must verify the contents of all addresses after complet-
ing the erase command. The microcomputer enters the erase
verify mode by inputting the verify address and command code
A0
ing edge of the WE input, and the command code is internally
latched at the rising edge of the WE input. When control signals
are input in the second cycle at the timing shown in Figure 70, the
M38869FFAHP/GP outputs the contents of the specified address
to the external.
Note: If any memory location where the contents have not been
Erase verify command
16
in the first cycle. The address is internally latched at the fall-
t
erased is found in the erase verify operation, execute the op-
eration of “erase
however, the user does not need to write data 00
locations before erasing.
AS
t
address
CS
Verify
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
t
WP
t
AH
t
DS
A0
___
16
t
t
DH
CH
MITSUBISHI MICROCOMPUTERS
t
WRR
erase verify” over again. In this case,
___
Erase verify
Verify data output
3886 Group
Dout
16
to memory