PIC18F8525-E/PT Microchip Technology, PIC18F8525-E/PT Datasheet - Page 58

• Manufacturer Part Number: PIC18F8525-E/PT
• Description: IC PIC MCU FLASH 24KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8525-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6525/6621/8525/8621
4.12
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
Indirect addressing is possible by using one of the INDF
registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation (NOP). The
FSR register contains a 12-bit address which is shown in
Figure 4-10.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 4-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-5:
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1.
2.
3.
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
DS39612B-page 56
NEXT
CONTINUE
FSR0: composed of FSR0H:FSR0L
FSR1: composed of FSR1H:FSR1L
FSR2: composed of FSR2H:FSR2L
LFSR
CLRF
BTFSS
GOTO
Indirect Addressing, INDF and
FSR Registers
FSR0, 0x100
POSTINC0
FSR0H, 1
NEXT
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
;
; Clear INDF
; register and
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
the
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
Status bits are not affected.
4.12.1
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers
determines how the FSR will be modified during
indirect addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
• Auto-decrement FSRn after an indirect access
• Auto-increment FSRn after an indirect access
• Auto-increment FSRn before an indirect access
• Use the value in the WREG register as an offset
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
Incrementing or decrementing an FSR affects all
12 bits. That is, when FSRnL overflows from an
increment, FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
Stack Pointer in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the signed value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register,
the write operation will dominate over the pre- or
post-increment/decrement functions.
change) – INDFn.
(post-decrement) – POSTDECn.
(post-increment) – POSTINCn.
(pre-increment) – PREINCn.
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn.
data
INDIRECT ADDRESSING
OPERATION
from
the
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address
pointed
to
by