PIC18F8525-E/PT Microchip Technology, PIC18F8525-E/PT Datasheet
PIC18F8525-E/PT
Specifications of PIC18F8525-E/PT
Available stocks
Related parts for PIC18F8525-E/PT
PIC18F8525-E/PT Summary of contents
Page 1
... PIC18F6525/6621/8525/8621 2005 Microchip Technology Inc. Data Sheet 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D DS39612B ...
Page 2
... PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... PIC18F8621 64K 32768 3840 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 External Memory Interface (PIC18F8525/8621 Devices Only): • Address capability Mbytes • 16-bit interface Analog Features: • 10-bit 16-channel Analog-to-Digital Converter (A/D): - Auto-Acquisition - Conversion available during Sleep • Programmable 16-level Low-Voltage Detection ...
Page 4
... ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set. 2: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. DS39612B-page PIC18F6525 PIC18F6621 RB0/INT0/FLT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1/PGM 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/ECCP1/P1A 2005 Microchip Technology Inc. ...
Page 5
... Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes. 2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is not set. 3: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 PIC18F8525 PIC18F8621 RJ2/WRL 60 RJ3/WRH 59 RB0/INT0/FLT0 ...
Page 6
... Appendix C: Conversion Considerations ........................................................................................................................................... 378 Appendix D: Migration From Mid-Range to Enhanced Devices......................................................................................................... 378 Appendix E: Migration From High-End to Enhanced Devices............................................................................................................ 379 Index .................................................................................................................................................................................................. 381 On-Line Support................................................................................................................................................................................. 391 Systems Information and Upgrade Hot Line ...................................................................................................................................... 391 Reader Response .............................................................................................................................................................................. 392 PIC18F6525/6621/8525/8621 Product Identification System ............................................................................................................ 393 DS39612B-page 4 2005 Microchip Technology Inc. ...
Page 7
... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 5 ...
Page 8
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 6 2005 Microchip Technology Inc. ...
Page 9
... EXTERNAL MEMORY INTERFACE In the unlikely event that 64 Kbytes of program memory is inadequate for an application, the PIC18F8525/8621 members of the family also implement an external memory interface. This allows the controller’s internal program counter to address a memory space MBytes, permitting a level of data access that few 8-bit devices can claim. ...
Page 10
... All other features for devices in the PIC18F6525/6621/ 8525/8621 family are identical. These are summarized in Table 1-1. for Block diagrams for PIC18F8525/8621 devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2. PIC18F6525 PIC18F6621 DC – 40 MHz DC – 40 MHz ...
Page 11
... ECCP3 CCP4 Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set. 2: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Data Bus<8> Data Latch 8 8 Data RAM (3 ...
Page 12
... PIC18F6525/6621/8525/8621 FIGURE 1-2: PIC18F8525/8621 BLOCK DIAGRAM Table Pointer<21> 21 inc/dec logic 21 20 PCLATU PCU Program Counter Address Latch Program Memory 31 Level Stack (48/64 Kbytes) Data Latch Table Latch 8 16 ROM Latch (4) AD15:AD0, A19:16 Instruction Decode and Control Power-up OSC2/CLKO Timer OSC1/CLKI Timing ...
Page 13
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 14
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 15
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 16
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 17
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 18
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 19
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 20
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 21
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 22
... I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices ...
Page 23
... OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The PIC18F6525/6621/8525/8621 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 2-1: (1) C1 OSC1 XTAL (2) ...
Page 24
... I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). ) and capacitor (C ) EXT EXT values. The user EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC18F6X2X/8X2X OSC2/CLKO /4 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT 2005 Microchip Technology Inc. ...
Page 25
... PLL Enable Phase Comparator OUT 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2.5 Phase Locked Loop (PLL) A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming oscillator signal by 4. For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz ...
Page 26
... See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 24.0 “Special Features of the CPU” for Configuration register details OSC 4 x PLL Sleep T OSC T1OSCEN Clock Enable Source Oscillator Clock Source Option for Other Modules Oscillator Switching Enable T SCLK 2005 Microchip Technology Inc. ...
Page 27
... ECIO+SPLL and HS+SPLL modes only; forced cleared for all other oscillator modes. 2: The setting of SCS0 = 1 supersedes SCS1 = 1. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note: The Timer1 oscillator must be enabled and operating to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON) ...
Page 28
... XT, LP), then the transition will take place after an oscillator start-up time (T timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes, is shown in Figure 2- OST T OSC has occurred. A OST SCS 2005 Microchip Technology Inc. ...
Page 29
... EC with PLL active, is shown in Figure 2-11. FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (EC WITH PLL ACTIVE, SCS1 = T1OSI OSC1 PLL Clock Input Internal System Clock SCS (OSCCON<0>) Program Counter PC 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 ) plus an OST PLL T OSC T SCS 1 2 ...
Page 30
... Then, the Oscillator Start-up Timer (OST) is invoked. However, this is still not a sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional fixed 2 ms (nominal) time-out to allow the PLL ample time to lock to the incoming clock frequency OSC2 Pin 2005 Microchip Technology Inc. ...
Page 31
... RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations as indicated in Table 3-2 ...
Page 32
... Function Registers, while Table 3-3 shows the Reset conditions for all of the registers. falls below parameter D005 for greater falls below DD rises above DD rises above then will keep DD DD drops below BV while the DD DD rises above BV , the Power- 2005 Microchip Technology Inc. ...
Page 33
... Brown-out Reset Interrupt Wake-up from Sleep Legend unchanged unknown Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0008h or 0018h). 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 (2) Power-up PWRTE = 1 (2) ...
Page 34
... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’ MCLR function is disabled, PORTG<5> read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode. DS39612B-page 32 ...
Page 35
... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’ MCLR function is disabled, PORTG<5> read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode. 2005 Microchip Technology Inc. ...
Page 36
... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’ MCLR function is disabled, PORTG<5> read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode. DS39612B-page 34 ...
Page 37
... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’ MCLR function is disabled, PORTG<5> read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode. 2005 Microchip Technology Inc. ...
Page 38
... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’ MCLR function is disabled, PORTG<5> read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode. DS39612B-page 36 ...
Page 39
... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 T PWRT T OST T PWRT T T PWRT T VIA 1 kΩ RESISTOR) DD ...
Page 40
... PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL DS39612B-page 38 VIA 1 kΩ RESISTOR PWRT T OST VIA 1 kΩ RESISTOR PWRT T OST T PLL 2005 Microchip Technology Inc. ...
Page 41
... Flash program memory and data EEPROM is provided in Section 5.0 “Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively. In addition to on-chip Flash, the PIC18F8525/8621 devices are also capable of accessing external program memory through an external memory bus. Depending on the selected operating mode (discussed in Section 4 ...
Page 42
... High Priority Interrupt Vector 000008h Low Priority Interrupt Vector 000018h On-Chip Flash Program Memory 00BFFFh 00C000h Read ‘0’ 1FFFFFh 200000h TABLE 4-1: MEMORY ACCESS FOR PIC18F8525/8621 PROGRAM MEMORY MODES Internal Program Memory Operating Mode Execution Table Read From Microprocessor No Access No Access Microprocessor Yes ...
Page 43
... PM1:PM0: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microcontroller with Boot Block mode 00 = Extended Microcontroller mode Note 1: This mode is available only on PIC18F8525/8621 devices. Legend Readable bit -n = Value after erase FIGURE 4-3: MEMORY MAPS FOR PIC18F6525/6621/8525/8621 PROGRAM MEMORY MODES ...
Page 44
... Pointer remains at ‘0’. The STKUNF bit will remain set until cleared in software or a POR occurs. Note: Returning a value of zero to the underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. stack 2005 Microchip Technology Inc. ...
Page 45
... POP instruction. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/C-0 U-0 R/W-0 ...
Page 46
... Instruction Register (IR) in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4- Execute INST (PC) Fetch INST ( Execute INST ( Internal Phase Clock Fetch INST ( 2005 Microchip Technology Inc. ...
Page 47
... Instruction 1: MOVLW Instruction 2: GOTO Instruction 3: MOVFF 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles ...
Page 48
... In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Note: The ADDWF update PCLATH and PCLATU. A read operation on PCL must be performed to update PCLATH and PCLATU. PCL instruction does not 2005 Microchip Technology Inc. ...
Page 49
... This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle regardless of the current BSR values, an Access Bank is implemented ...
Page 50
... Access RAM high (SFRs) FFh When ‘a’ the BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). 2005 Microchip Technology Inc. ...
Page 51
... BSR FC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6525/6621 devices and reads as ‘0’. 3: This is not a physical register. 4: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Name Address Name (3) INDF2 FBFh ...
Page 52
... F60h F40h — Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6525/6621 devices and reads as ‘0’. 3: This is not a physical register. 4: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 50 Name Address Name (1) (1) — F3Fh — (1) (1) — ...
Page 53
... INT1IE INT3IF — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 — — Bank Select Register PIC18F8525/8621 devices. Value on Details Bit 1 Bit 0 POR, BOR on page: 32, 42 ---0 0000 32, 42 0000 0000 ...
Page 54
... DC1B0 CCP1M3 CCP1M2 CCP1M1 DC2B0 CCP2M3 CCP2M2 CCP2M1 DC2B0 CCP3M3 CCP3M2 CCP3M1 PSS1AC1 PSS1AC0 PSS1BD1 CVRSS CVR3 CVR2 CVR1 PIC18F8525/8621 devices. Value on Details Bit 0 POR, BOR on page: N/A 56 N/A 56 33, 56 33, 56 xxxx xxxx C 33, 58 ---x xxxx 33, 133 0000 0000 33, 133 xxxx xxxx ...
Page 55
... SSPIF CCP1IF TX1IE SSPIE CCP1IE WAIT0 — — — Data Direction Control Register for PORTG — Read PORTG Data Latch, Write PORTG Data Latch (1) PIC18F8525/8621 devices. Value on Details Bit 1 Bit 0 POR, BOR on page: CM1 CM0 34, 243 0000 0000 34, 145 xxxx xxxx ...
Page 56
... CCP5M2 SYNC SENDB BRGH CREN ADDEN FERR PSS3AC1 PSS3AC0 P3DC4 P3DC3 P3DC2 PSS2AC1 PSS2AC0 P2DC4 P2DC3 P2DC2 PIC18F8525/8621 devices. Value on Details Bit 1 Bit 0 POR, BOR on page: 35, 127 xxxx xxxx 35, 124 0000 xxxx 36, 121 --xx xxxx 36, 119 x000 0000 36, 116 xxxx xxxx 36, 113 ...
Page 57
... Note 1: For register file map detail, see Table 4-2. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 4.11 Bank Select Register (BSR) The need for a large general purpose memory space dictates a RAM banking scheme ...
Page 58
... INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (Status bits are not affected indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions. 2005 Microchip Technology Inc ...
Page 59
... INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 4-10: INDIRECT ADDRESSING 11 Location Select Note 1: For register file map detail, see Table 4-2. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 0h RAM Address FFFh 12 File Address = Access of an Indirect Addressing Register File FSR ...
Page 60
... The C and DC bits operate as the borrow and digit borrow bits respectively in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown 2005 Microchip Technology Inc. ...
Page 61
... A Brown-out Reset has not occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected ...
Page 62
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 60 2005 Microchip Technology Inc. ...
Page 63
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 5.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 64
... The inability to clear the WR bit in software prevents the accidental or premature termination of a write When set, operation. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. Table Latch (8-bit) TABLAT 2005 Microchip Technology Inc. ...
Page 65
... Initiates an EEPROM read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-0 R/W-x — FREE ...
Page 66
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 WRITE – TBLPTR<21:3> READ – TBLPTR<21:0> TBLPTRL 0 2005 Microchip Technology Inc. ...
Page 67
... WORD_EVEN TBLRD*+ MOVFW TABLAT, W MOVWF WORD_ODD 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 68
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write AAh ; start erase (CPU stall) ; re-enable interrupts 2005 Microchip Technology Inc. ...
Page 69
... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write ...
Page 70
... TBLWT holding register. ; loop until buffers are full 2005 Microchip Technology Inc. ...
Page 71
... Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to device configuration bits. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 72
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 70 2005 Microchip Technology Inc. ...
Page 73
... PIC18C601/801 micro- controllers. The most notable difference is that the interface on PIC18F8525/8621 devices only operates in 16-bit modes. The 8-bit mode is not supported. For a more complete discussion of the operating modes that use the external memory interface, refer to Section 4.1.1 “ ...
Page 74
... At that time, the pins will change from external bus to I/O ports. TABLE 6-1: PIC18F8525/8621 EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit RD0/AD0 ...
Page 75
... BYTE WRITE MODE Figure 6-1 shows an example of 16-bit Byte Write mode for PIC18F8525/8621 devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories ...
Page 76
... WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8525/8621 devices. This mode is used for word-wide memories which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word- wide external memories ...
Page 77
... BYTE SELECT MODE Figure 6-3 shows an example of 16-bit Byte Select mode for PIC18F8525/8621 devices. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle ...
Page 78
... TBLRD Cycle 0Ch CF33h Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 0Ch 9256h ‘1’ ‘1’ ‘0’ Wait 9256h Opcode Fetch ADDLW 55h from 000104h MOVLW 2005 Microchip Technology Inc. ...
Page 79
... EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE 00h A<19:16> AD<15:0> 0003h 3AAAh CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Bus Inactive DS39612B-page 77 ...
Page 80
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 78 2005 Microchip Technology Inc. ...
Page 81
... The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to parameter D122 (Section 27.0 “Electrical Characteristics”) for exact limits. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 7.1 EEADR and EEADRH The address register pair can address maximum of 1024 bytes of data EEPROM ...
Page 82
... Does not initiate an EEPROM read Legend Readable bit -n = Value at POR DS39612B-page 80 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2005 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
Page 83
... EECON1, WR BSF INTCON, GIE BCF EECON1, WREN 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 control bit (EECON1<6>) and then set the RD control bit (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation) ...
Page 84
... Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts 2005 Microchip Technology Inc. ...
Page 85
... IPR2 — CMIP — PIR2 — CMIF — PIE2 — CMIE — Legend unknown unchanged, — = unimplemented, read as ‘ 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF — — — EE Addr Register High ---- --00 FREE ...
Page 86
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 84 2005 Microchip Technology Inc. ...
Page 87
... Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 8.2 Operation Example 8-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
Page 88
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H 2005 Microchip Technology Inc. ...
Page 89
... Individual interrupts can be disabled through their corresponding enable bits. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 90
... INT1IP INT2IF INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE GIEL/PEIE RBIP GIE/GEIH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2005 Microchip Technology Inc. Wake- Sleep mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h ...
Page 91
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 92
... This feature allows for software polling. DS39612B-page 90 R/W-1 R/W-1 R/W-1 INTEDG1 INTEDG2 INTEDG3 TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2005 Microchip Technology Inc. ...
Page 93
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/W-0 R/W-0 ...
Page 94
... PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit read or a write operation has taken place (must be cleared in software read or write has occurred Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. bit 6 ADIF: A/D Converter Interrupt Flag bit A/D conversion completed (must be cleared in software) ...
Page 95
... Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-0 R/W-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 96
... R = Readable bit -n = Value at POR DS39612B-page 94 U-0 R-0 R-0 R/W-0 — RC2IF TX2IF TMR4IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCP5IF CCP4IF CCP3IF bit Bit is unknown 2005 Microchip Technology Inc. ...
Page 97
... PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt ...
Page 98
... Legend Readable bit -n = Value at POR DS39612B-page 96 U-0 R/W-0 R/W-0 R/W-0 — EEIE BCLIE LVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2005 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
Page 99
... Disables the TMR4 to PR4 match interrupt bit 2-0 CCPxIE: CCPx Interrupt Enable bit (ECCP3, CCP4 and CCP5 Enables the CCPx interrupt 0 = Disables the CCPx interrupt Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-0 R/W-0 R/W-0 — RC2IE ...
Page 100
... ADIP bit 7 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority Note: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: USART1 Receive Interrupt Priority bit ...
Page 101
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-1 R/W-1 — EEIP BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 102
... Value at POR DS39612B-page 100 U-0 R/W-1 R/W-1 R/W-1 — RC2IP TX2IP TMR4IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 CCP5IP CCP4IP CCP3IP bit Bit is unknown 2005 Microchip Technology Inc. ...
Page 103
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-4. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 U-0 R/W-1 R-1 — — ...
Page 104
... Depending on the user’s application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS 2005 Microchip Technology Inc. ...
Page 105
... Q WR LAT + WR Port CK Data Latch Data Bus RD Port 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 10.1 PORTA, TRISA and LATA Registers PORTA is a 7-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 106
... I/O pins have protection diodes to V and Data Latch TRIS Latch Q and BLOCK DIAGRAM OF RA4/T0CKI PIN (1) I/O pin N Data Latch Schmitt CK Q Trigger TRIS Latch Input Buffer and (1) N I/O pin V SS TTL Input Buffer D EN 2005 Microchip Technology Inc. ...
Page 107
... Shaded cells are not used by PORTA. Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Input/output or analog input. Input/output or analog input. ...
Page 108
... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. For PIC18F8525/8621 devices, RB3 can be configured by the configuration bit, CCP2MX, as the alternate peripheral pin for the ECCP2 module. This is only available ...
Page 109
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: For PIC18F8525/8621 parts, the ECCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode. ...
Page 110
... This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: Valid for PIC18F8525/8621 devices in all operating modes except Microcontroller mode when CCP2MX is not set. RC1 is the default assignment for ECCP2/PA2 when CCP2MX is set in all devices; RE7 is the alternate assignment for PIC18F8525/8621 devices in Microcontroller mode when CCP2MX is clear. ...
Page 111
... RD PORTC Peripheral Data In Note 1: I/O pins have diode protection Peripheral output enable is only active if peripheral select is active. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. ...
Page 112
... Valid when CCP2MX is set in all devices and in all operating modes (default). RE7 is the alternate assignment for ECCP2/P2A for all PIC18F6525/6621 devices and PIC18F8525/8621 devices in Microcontroller modes when CCP2MX is not set; RB3 is the alternate assignment for PIC18F8525/8621 devices in all other operating modes. ...
Page 113
... LATD ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 10-9: RD LATD Data Bus D WR LATD or PORTD CK Data Latch D WR TRISD ...
Page 114
... RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V DS39612B-page 112 Port Data 1 CK Data Latch TRIS Latch and (1) I/O pin TTL Input Buffer 2005 Microchip Technology Inc. ...
Page 115
... Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. 2: External memory interface functions are only available on PIC18F8525/8621 devices. TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 ...
Page 116
... ECCP2 module when the device is operating in Microcontroller mode. This is done by clearing the configuration bit, CCP2MX, in the CONFIG3H Configuration register (CONFIG3H<0>). Note: For PIC18F8525/8621 (80-pin) devices operating in Extended Microcontroller mode, PORTE defaults to the system bus is also on Power-on Reset. EXAMPLE 10-5: ...
Page 117
... RD PORTE RD LATE Data Bus WR LATE or PORTE WR TRISE RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 I/O pin TRIS Override Pin RE0 Schmitt ...
Page 118
... Valid for all PIC18F6525/6621 devices and PIC18F8525/8621 devices in Microcontroller mode when CCP2MX is not set. RC1 is the default assignment for ECCP2/P2A for all devices in Microcontroller mode when CCP2MX is set; RB3 is the alternate assignment for PIC18F8525/8621 devices in operating modes except Microcontroller mode when CCP2MX is not set. ...
Page 119
... D WR LATF PORTF Data Latch D WR TRISF CK TRIS Latch RD TRISF RD PORTF To A/D Converter Note 1: I/O pins have diode protection to V 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 EXAMPLE 10-6: CLRF PORTF CLRF LATF MOVLW 0x07 MOVWF CMCON MOVLW 0x0F MOVWF ADCON1 ; Set PORTF as digital I/O ...
Page 120
... I/O pin WR TRISF Input Buffer D RD PORTF SS Input Note: I/O pins have diode protection to V and RF7 PIN BLOCK DIAGRAM D Q I/O pin CK Data Latch D Q Schmitt Trigger CK Input Buffer TRIS Latch TTL Input Buffer RD TRISF and 2005 Microchip Technology Inc. ...
Page 121
... C2OUT C1OUT C2INV CVRCON CVREN CVROE CVRR CVRSS Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Function Input/output port pin or analog input. Input/output port pin, analog input or Comparator 2 output. ...
Page 122
... RG4:RG3 as inputs TRIS OVERRIDE Override Peripheral Yes ECCP3 I/O Yes USART1 Async Xmit, Sync Clock Yes USART1 Async Rcv, Sync Data Out Yes CCP4 I/O Yes CCP5 I/O DD and Peripheral output enable is only active if peripheral select is active. 2005 Microchip Technology Inc. ...
Page 123
... LATG — — — TRISG — — — Legend unknown unchanged, — = unimplemented, read as ‘0’ Note 1: RG5 is available as an input only when MCLR is disabled. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Schmitt Trigger Latch Filter Low-Level MCLR Detect Input/output port pin, Enhanced Capture 3 input/Compare 3 output/ PWM 3 output or Enhanced PWM 3 output P3A ...
Page 124
... PIC18F6525/6621/8525/8621 10.8 PORTH, LATH and TRISH Registers Note: PORTH is available only on PIC18F8525/ 8621 devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 125
... RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTH RD LATH Data Bus WR LATH or PORTH WR TRISH RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to V 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Port Data 1 CK Data Latch ...
Page 126
... Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. 2: Valid only for PIC18F8525/8621 devices when ECCPMX is not set. The alternate assignments for P1B/P1C/P3B/P3C in all PIC18F6525/6621 devices and in PIC18F8525/8621 devices when ECCPMX is set are RE6, RE5, RE4 and RE3, respectively. ...
Page 127
... PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on PIC18F8525/ 8621 devices. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 128
... UB/LB Out System Bus Control Drive System Note 1: I/O pins have diode protection to V DS39612B-page 126 Port Data 1 CK Data Latch TRIS Latch and Port Data 1 CK Data Latch TRIS Latch and (1) I/O pin (1) I/O pin 2005 Microchip Technology Inc. ...
Page 129
... LATJ LATJ Data Output Register TRISJ Data Direction Control Register for PORTJ Legend unknown unchanged 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Function Input/output port pin or address latch enable control for external memory interface. Input/output port pin or output enable control for external memory interface ...
Page 130
... Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. Note: For PIC18F8525/8621 devices, the Parallel Slave Port is available Microcontroller mode. The PSP can directly interface to an 8-bit micro- processor data bus ...
Page 131
... PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. Legend Readable bit -n = Value at POR FIGURE 10-25: PARALLEL SLAVE PORT WRITE WAVEFORMS ...
Page 132
... PIE1 PSPIE ADIE RC1IE (1) IPR1 PSPIP ADIP RC1IP Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 130 Bit 4 Bit 3 Bit 2 Bit 1 PSPMODE — ...
Page 133
... Prescale value 000 = 1:2 Prescale value Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 134
... T0PS2, T0PS1, T0PS0 1 Sync with Internal TMR0L Clocks Delay PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2005 Microchip Technology Inc. ...
Page 135
... Legend unknown unchanged, — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 11.2.1 SWITCHING PRESCALER ...
Page 136
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 134 2005 Microchip Technology Inc. ...
Page 137
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 138
... TMR1CS 8 ECCP Special Event Trigger TMR1 CLR TMR1L TMR1ON On/Off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized 0 Clock Input 1 Synchronize det 2 Sleep Input Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Sleep Input 2005 Microchip Technology Inc. ...
Page 139
... Capacitor values are for design guidance only. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 12.3 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1< ...
Page 140
... Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt ; Preload for 1 sec overflow ; Clear interrupt flag ; Increment seconds ; 60 seconds elapsed? ; No, done ; Clear seconds ; Increment minutes ; 60 minutes elapsed? ; No, done ; clear minutes ; Increment hours ; 24 hours elapsed? ; No, done ; Reset hours Done 2005 Microchip Technology Inc. ...
Page 141
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Bit 4 ...
Page 142
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 140 2005 Microchip Technology Inc. ...
Page 143
... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the ECCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 144
... PR2 Timer2 Period Register Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 142 13.3 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate the shift clock ...
Page 145
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP/ECCP clock source. ...
Page 146
... Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 ECCP Special Event Trigger T3CCPx TMR3 CLR TMR3L TMR3ON On/Off OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Synchronized 0 Clock Input 1 Synchronize det 2 Sleep Input Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 Sleep Input 2005 Microchip Technology Inc. ...
Page 147
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 14.4 Resetting Timer3 Using an ECCP Special Trigger Output If either the ECCP1 or ECCP2 module is configured in ...
Page 148
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 146 2005 Microchip Technology Inc. ...
Page 149
... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 15.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
Page 150
... CCP5IE CCP4IE Sets Flag bit TMR4IF Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u CCP3IP --11 1111 --00 0000 CCP3IF --00 0000 --00 0000 CCP3IE --00 0000 --00 0000 0000 0000 0000 0000 1111 1111 1111 1111 2005 Microchip Technology Inc. ...
Page 151
... Reserved 11xx = PWM mode Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. The operations of PWM mode described in Section 16.4 “PWM Mode” apply to CCP4 and CCP5 only ...
Page 152
... Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. 2005 Microchip Technology Inc. ...
Page 153
... Prescaler ÷ RG3/CCP4/P1D pin and Edge Detect CCP1CON<3:0> Q’s 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP4IE (PIE3<1>) clear to avoid false interrupts and should clear the flag bit, CCP4IF, following any such change in operating mode ...
Page 154
... CCP5; they are only available on ECCP1 and ECCP2. Their operation is discussed in detail in Section 17.2.1 “Special Event Trigger”. Set Flag bit CCP4IF Output Logic Match CCP4CON<3:0> Mode Select TMR1H CCPR4H CCPR4L Comparator 0 1 T3CCP2 TMR1L TMR3H TMR3L 2005 Microchip Technology Inc. ...
Page 155
... CCP5CON — — DC5B1 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Compare, Timer1 or Timer3. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE ...
Page 156
... PWM operation. When the CCPR4H and 2-bit latch match TMR2, con- catenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP4 pin is cleared. • OSC (TMR2 Prescale Value) T • (TMR2 Prescale Value) OSC 2005 Microchip Technology Inc. ...
Page 157
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 16.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. ...
Page 158
... Capture/Compare/PWM Register 5 High Byte CCP5CON — — DC5B1 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 156 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF ...
Page 159
... Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Capture and Compare functions of the ECCP module are the same as the standard CCP module. The prototype control register for the Enhanced CCP module is shown in Register 17-1 ...
Page 160
... Dual PWM 10xx 11xx Quad PWM x1xx 11xx PIC18F8525/8621 devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP ECCP1 00xx 11xx Legend Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. ...
Page 161
... RB3/INT3 00xx 11xx Dual PWM RB3/INT3 10xx 11xx Quad PWM RB3/INT3 x1xx 11xx PIC18F8525/8621 devices, CCP2MX = 0, all other Program Memory modes: Compatible CCP ECCP2 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx Legend Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. ...
Page 162
... The Timer2 postscaler (see Section 13.0 or “Timer2 Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. ). OSC • OSC (TMR2 Prescale Value) 2005 Microchip Technology Inc. ...
Page 163
... In PWM mode, CCPR1H is a read-only register. TABLE 17-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 P1M1<1:0> CCP1M<3:0> ECCP1/P1A P1B Output R ...
Page 164
... Section 17.4 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 17-2. 0 Duty Cycle Period Delay Delay 2005 Microchip Technology Inc. PR2 + 1 ...
Page 165
... Dead-Band Delay” for more details on dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the TRISC<2> and TRISE<6> bits must be cleared to configure P1A and P1B as outputs. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 0 Duty Cycle Period ...
Page 166
... EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) PIC18F6X2X/8X2X Half-Bridge Output Driving a Full-Bridge Circuit PIC18F6X2X/8X2X P1A P1B DS39612B-page 164 V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver FET Driver FET Driver 2005 Microchip Technology Inc. ...
Page 167
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. The TRISC<2>, TRISC<6:5> and TRISG<4> ...
Page 168
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD 2005 Microchip Technology Inc. ...
Page 169
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 (1) Period DC , depending on the Timer2 prescaler value. The modulated P1B and P1D signals OSC ...
Page 170
... OSC OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared are selected using the bits (bits<6:4> of the PSS1AC1:PSS1AC0 and R/W-0 R/W-0 PxDC1 PxDC0 bit Bit is unknown 2005 Microchip Technology Inc. ...
Page 171
... PSSxBD1:PSSxBD0: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to ‘0’ Drive Pins B and D to ‘1’ Pins B and D tri-state Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/W-0 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 172
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Resumes ECCPASE Cleared by Firmware PWM Resumes 2005 Microchip Technology Inc. ...
Page 173
... PSS1BD1:PSS1BD0 bits. • Set the ECCP1ASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 8. If auto-restart operation is required, set the P1RSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: • ...
Page 174
... ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 ECCP3DEL Px3RSEN P3DC6 P3DC5 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 172 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF ...
Page 175
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
Page 176
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2005 Microchip Technology Inc. ...
Page 177
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC ...
Page 178
... SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit 2005 Microchip Technology Inc. ...
Page 179
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3.4 TYPICAL CONNECTION Figure 18-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
Page 180
... This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 18-3 shows the waveforms for Master mode. bit 2 bit 5 bit 4 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ 2005 Microchip Technology Inc. ...
Page 181
... SSPIF Interrupt Flag SSPSR to SSPBUF 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output ...
Page 182
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39612B-page 180 bit 6 bit 3 bit 2 bit 5 bit 4 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ 2005 Microchip Technology Inc. ...
Page 183
... CKE D/A Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3.10 BUS MODE COMPATIBILITY Table 18-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
Page 184
... SSPBUF Addr Match and the SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. 2005 Microchip Technology Inc. ...
Page 185
... SSPBUF is empty In Receive mode SSPBUF is full (does not include the ACK and Stop bits SSPBUF is empty (does not include the ACK and Stop bits) Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2 C MODE) R-0 R-0 R-0 D/A ...
Page 186
... SSPEN CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown 2005 Microchip Technology Inc. ...
Page 187
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2 C MODE) R/W-0 R/W-0 R/W-0 ...
Page 188
... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 2005 Microchip Technology Inc. ...
Page 189
... The clock must be released by setting bit CKP (SSPCON<4>). See Section 18.4.4 “Clock Stretching” for more detail. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 190
... PIC18F6525/6621/8525/8621 2 FIGURE 18-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39612B-page 188 2005 Microchip Technology Inc. ...
Page 191
... FIGURE 18-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 189 ...
Page 192
... PIC18F6525/6621/8525/8621 2 FIGURE 18-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39612B-page 190 2005 Microchip Technology Inc. ...
Page 193
... FIGURE 18-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 191 ...
Page 194
... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 18-11). 2005 Microchip Technology Inc. ...
Page 195
... SDA DX SCL CKP WR SSPCON 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 18-12) ...
Page 196
... PIC18F6525/6621/8525/8621 2 FIGURE 18-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39612B-page 194 2005 Microchip Technology Inc. ...
Page 197
... FIGURE 18-14: I C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 195 ...
Page 198
... UA bit will not is enabled be set and the slave will begin receiving data after the Acknowledge (Figure 18-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ 2005 Microchip Technology Inc. ...
Page 199
... Generate a Stop condition on SDA and SCL. FIGURE 18-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 200
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. 2005 Microchip Technology Inc. ...