PIC18F8525-E/PT Microchip Technology, PIC18F8525-E/PT Datasheet
PIC18F8525-E/PT
Specifications of PIC18F8525-E/PT
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PIC18F8525-E/PT Summary of contents
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... FLASH Microcontroller Programming Specification 1.0 DEVICE OVERVIEW This document includes the programming specifications for the following devices: • PIC18F6525 • PIC18F6621 • PIC18F8525 • PIC18F8621 2.0 PROGRAMMING OVERVIEW OF THE PIC18F6X2X/8X2X PIC18F6X2X/8X2X devices can be programmed using either the high voltage In-Circuit Serial Programming ...
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... PP 7 RG4/CCP5/P1D RF7/SS 11 RF6/AN11/C1IN- 12 RF5/AN10/C1IN+/CV REF 13 RF4/AN9/C2IN- 14 RF3/AN8/C2IN+ 15 RF2/AN7/C1OUT 16 Note 1: The CCP2 pin placement depends on the CCP2MX fuse setting. DS30499B-page PIC18F6525 PIC18F6621 RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1/PGM 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1/P1A 2003 Microchip Technology Inc. ...
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... RH7/AN15/P1B 19 (2) RH6/AN14/P1C Note 1: The CCP2 pin placement depends on the CCP2MX fuse and Processor mode settings. 2: P1B, P1C, P3B, and P3C pin placement depends on the ECCPMUX fuse setting. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X PIC18F8525 PIC18F8621 RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 57 RB2/INT2 ...
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... Read as ‘0’ 1FFFFFh Configuration and ID Space 3FFFFFh Note: Sizes of memory areas not to scale. DS30499B-page 4 TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Device blocks. PIC18F6525 PIC18F8525 PIC18F6621 PIC18F8621 MEMORY SIZE/DEVICE 64 Kbytes 48 Kbytes (PIC18FX621) (PIC18FX525) Boot Block Boot Block Block 1 Block 2 Block 3 Block 4 Unimplemented Unimplemented Read ‘ ...
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... Configuration and ID Space 2FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 2.3.1 MEMORY ADDRESS POINTER Memory in the address space 0000000h to 3FFFFFh is addressed via the Table Pointer register, which is comprised of three Pointer registers: • TBLPTRU, at RAM address 0FF8h • ...
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... Program Memory Program IDs Program Data Verify Program Verify IDs Verify Data Program Configuration Bits Verify Configuration Bits Done FIGURE 2-7: ENTERING LOW VOLTAGE PROGRAM/ VERIFY MODE P15 P12 V IH MCLR PGM PGD PGC PGD = Input 2003 Microchip Technology Inc. ...
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... PGC PGD 4-bit Command 2003 Microchip Technology Inc. PIC18F6X2X/8X2X TABLE 2-3: Core Instruction (Shift in16-bit instruction) Shift out TABLAT register Table Read Table Read, post-increment Table Read, post-decrement Table Read, pre-increment Table Write Table Write, post-increment by 2 Table Write, post-decrement by 2 ...
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... Write 80h TO 3C0004h to erase entire device NOP 00 00 Hold PGD low until erase completes. BULK ERASE FLOW Start Load Address Pointer to 3C0004h Write 80h To Erase Entire Device Delay P11+P10 Time Done P10 P11 16-bit Erase Time Data Payload 2003 Microchip Technology Inc. ...
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... Sections 3.1.2 and 3.2. determined that a data EEPROM erase must be performed at a supply voltage below the bulk erase limit, follow the methodology described in Section 3.3 and write ‘1’s to the array. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X 3.1.2 ICSP MULTI-PANEL SINGLE ROW ERASE ...
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... Write 2 dummy bytes and start programming. NOP - hold PGC high for time P9. Start Addr = 0 Configure Device for Multi-Panel Erase Start Erase Sequence and hold PGC High Until Done Delay P9 + P10 Time for Erase to Occur All No Panels Done? Yes Done 2003 Microchip Technology Inc. ...
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... Figure 3-4). Multi-Panel Write mode is enabled by appropriately configuring the Programming Control register located at 3C0006h. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X The programming duration is externally timed and is controlled by PGC. After a “Start Programming” com- mand is issued (4-bit command, ‘ ...
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... Panel 1 TBLPTR<21:13> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> Offset = TBLPTR<12:3> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. DS30499B-page 12 Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> 2003 Microchip Technology Inc. ...
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... To continue writing data, repeat steps 2 through 5, where the address pointer is incremented each panel at each iteration of the loop. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS BSF EECON1, WREN ...
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... All No Panel Buffers Written? Yes Start Write Sequence and Hold PGC High Until Done Delay P9+P10 Time for Write to Occur All No Locations Done? Yes Done P5A 4-bit Command PGD = Input P10 16-bit Programming Time Data Payload 2003 Microchip Technology Inc. ...
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... In this case, however assumed that the address space to be written already has data in it (i.e not blank). 2003 Microchip Technology Inc. PIC18F6X2X/8X2X The minimum amount of code memory that may be erased at a given time is 64 bytes. Again, the device must be placed in Single Panel Write mode ...
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... MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold PGC high for time P9 BCF EECON1, WREN 2003 Microchip Technology Inc. ...
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... PGC PGD 4-bit Command BSF EECON1 PGC Poll WR bit PGD 4-bit Command 2003 Microchip Technology Inc. PIC18F6X2X/8X2X FIGURE 3-7: P5A P11A Poll WR bit, Repeat Until Clear (see below) PGD = Input P5A 4-bit Command MOVF EECON1 PGD = Input PROGRAM DATA FLOW ...
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... EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH MOVLW <Data> MOVWF EEDATA BSF EECON1, WREN MOVLW 0X55 MOVWF EECON2 MOVLW 0XAA MOVWF EECON2 BSF EECON1, WR MOVF EECON1 MOVWF TABLAT (1) Shift out data BCF EECON1, WREN 2003 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F6X2X/8X2X Note: Even though multi-panel writes are dis- abled, the user must still fill the 8-byte data buffer for the panel. Table 3-7 demonstrates the code sequence required to write the ID locations ...
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... MOVLW 00h MOVWF TBLPRTH MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 INCF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 four between every NOPs 2003 Microchip Technology Inc. ...
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... FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW Start Load Even Configuration Address Program LSB Delay P9 Time for Write Execute four NOPs Done 2003 Microchip Technology Inc. PIC18F6X2X/8X2X Start Load Odd Configuration Address Program MSB Delay P9 Time for Write Execute four NOPs Done ...
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... ID and Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output P5A MSb Fetch Next 4-bit Command PGD = Input 2003 Microchip Technology Inc. ...
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... All No Code Memory Verified? Yes 2003 Microchip Technology Inc. PIC18F6X2X/8X2X The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code mem- ory has been verified. The post-increment feature of the table read 4-bit command may not be used to incre- ment the Table Pointer beyond the code memory space ...
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... EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT (1) Shift Out Data READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data Done ? Yes Done 2003 Microchip Technology Inc. ...
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... Refer to Table 5-2 for blank configuration expect data for the various PIC18F6X2X/8X2X devices. Given that “Blank Checking” is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 and Section 4.2 for implementation details. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X ...
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... Low Voltage Programming (CONFIG4L<2> make certain that RB5/PGM is held low during entry into ICSP. Device ID Value DEVID2 0Ah 111x xxxx 0Ah 101x xxxx 0Ah 110x xxxx 0Ah 100x xxxx 2003 Microchip Technology Inc. . Once the LVP bit is IHH to the MCLR/V IHH PP DEVID1 ...
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... Unimplemented in PIC18F6X2X devices; maintain this bit set. 2: Unimplemented in PIC18FX525 devices; maintain this bit set MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X Bit 5 Bit 4 Bit 3 Bit 2 OSCSEN — ...
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... LP oscillator Brown-out Reset Voltage bits set to 2.0V BOR set to 2.7V BOR set to 4.2V BOR set to 4.5V BOR Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled 2003 Microchip Technology Inc. ...
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... Unimplemented in PIC18F6X2X devices; maintain this bit set. 2: Unimplemented in PIC18FX525 devices; maintain this bit set MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X Description Watchdog Timer Postscaler Select bits 1111 = 1:32768 1110 = 1:16384 ...
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... Table Write Protection bit (code memory area 8000h - BFFFh Code memory not write protected 0 = Code memory write protected Table Write Protection bit (code memory area C000h - FFFFh Code memory not write protected 0 = Code memory write protected 2003 Microchip Technology Inc. ...
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... Unimplemented in PIC18FX525 devices; maintain this bit set MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X Description Table Write Protection bit (data EEPROM Data EEPROM not write protected ...
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... EEPROM information must be included. An option to not include the data EEPROM information may be pro- vided. When embedding data EEPROM information in the HEX file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. DS30499B-page 32 5.6 ...
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... Legend: Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND 2003 Microchip Technology Inc. PIC18F6X2X/8X2X Checksum 0xAA at 0 Blank and Max Value Address 4642 4598 4E12 4DC7 ...
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... PIC18F8525 (CONFIG7L & 00FF)+(CONFIG7H & 0040)+SUM(IDs) Boot/ SUM(8000:BFFF)+(CONFIG1L & 0000)+(CONFIG1H & 002F)+ Block1/ (CONFIG2L & ...
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... HS/PLL mode only) + 1.5 µs (for EC mode only) where T is the instruction cycle time For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. 2003 Microchip Technology Inc. PIC18F6X2X/8X2X Min Max 9.00 13 ...
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... PIC18F6X2X/8X2X NOTES: DS30499B-page 36 2003 Microchip Technology Inc. ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 2003 Microchip Technology Inc. ...