PIC18F8525-E/PT Microchip Technology, PIC18F8525-E/PT Datasheet - Page 32

• Manufacturer Part Number: PIC18F8525-E/PT
• Description: IC PIC MCU FLASH 24KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8525-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6525/6621/8525/8621
3.1
A Power-on Reset pulse is generated on-chip when
V
circuitry, tie the MCLR pin through a 1 kΩ to 10 kΩ
resistor to V
components usually needed to create a Power-on
Reset delay. A minimum rise rate for V
(parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
Reset
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 3-2:
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter 33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows V
acceptable level. A configuration bit is provided to
enable/disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to V
parameter 33 for details.
DS39612B-page 30
DD
Note 1:
DD
rise is detected. To take advantage of the POR
, temperature and process variation. See DC
condition),
D
2:
3:
Power-on Reset (POR)
Power-up Timer (PWRT)
V
External Power-on Reset circuit is required
only if the V
The diode D helps discharge the capacitor
quickly when V
R < 40 kΩ is recommended to make sure
that the voltage drop across R does not
violate the device’s electrical specification.
R1 = 1 kΩ to 10 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/V
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
DD
DD
R
C
. This will eliminate external RC
device
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
R1
DD
power-up slope is too slow.
DD
powers down.
MCLR
operating
PIC18F6X2X/8X2X
DD
PP
POWER-UP)
DD
pin breakdown,
DD
to rise to an
parameters
is specified
3.3
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delays after the
PWRT delay is over (parameter 32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
3.4
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T
start-up time-out.
3.5
A configuration bit, BOR, can disable (if clear/
programmed) or enable (if set) the Brown-out Reset
circuitry. If V
than parameter 35, the brown-out situation will reset
the chip. A Reset may not occur if V
parameter D005 for less than parameter 35. The chip
will remain in Brown-out Reset until V
BV
invoked after V
the chip in Reset for an additional time delay
(parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay.
3.6
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18F6525/6621/8525/
8621 device operating in parallel.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all of the registers.
PLL
DD
) is typically 2 ms and follows the oscillator
. If the Power-up Timer is enabled, it will be
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
Time-out Sequence
DD
DD
falls below parameter D005 for greater
DD
rises above BV
DD
rises above BV
 2005 Microchip Technology Inc.
drops below BV
DD
DD
; it then will keep
DD
, the Power-up
DD
DD
rises above
falls below
while the