PIC18F8525-E/PT Microchip Technology, PIC18F8525-E/PT Datasheet - Page 391

• Manufacturer Part Number: PIC18F8525-E/PT
• Description: IC PIC MCU FLASH 24KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8525-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer0 ............................................................................... 131
Timer1 ............................................................................... 135
Timer2 ............................................................................... 141
Timer3 ............................................................................... 143
Timer4 ............................................................................... 147
Timing Diagrams
 2005 Microchip Technology Inc.
16-Bit Mode Timer Reads and Writes....................... 133
Associated Registers ................................................ 133
Clock Source Edge Select (T0SE Bit)....................... 133
Clock Source Select (T0CS Bit)................................ 133
Operation .................................................................. 133
Overflow Interrupt ..................................................... 133
Prescaler. See Prescaler, Timer0.
16-Bit Read/Write Mode............................................ 137
Associated Registers ................................................ 139
Operation .................................................................. 136
Oscillator ........................................................... 135, 137
Overflow Interrupt ............................................. 135, 137
Special Event Trigger (ECCP) .......................... 137, 160
TMR1H Register ....................................................... 135
TMR1L Register........................................................ 135
Use as a Real-Time Clock ........................................ 138
Associated Registers ................................................ 142
MSSP Clock Shift.............................................. 141, 142
Operation .................................................................. 141
Postscaler. See Postscaler, Timer2.
PR2 Register............................................. 141, 154, 160
Prescaler. See Prescaler, Timer2.
TMR2 Register.......................................................... 141
TMR2 to PR2 Match Interrupt ........... 141, 142, 154, 160
Associated Registers ................................................ 145
Operation .................................................................. 144
Oscillator ........................................................... 143, 145
Overflow Interrupt ............................................. 143, 145
Special Event Trigger (ECCP) .................................. 145
TMR3H Register ....................................................... 143
TMR3L Register........................................................ 143
Associated Registers ................................................ 148
MSSP Clock Shift...................................................... 148
Operation .................................................................. 147
Postscaler. See Postscaler, Timer4.
PR4 Register............................................................. 147
Prescaler. See Prescaler, Timer4.
TMR4 Register.......................................................... 147
TMR4 to PR4 Match Interrupt ........................... 147, 148
A/D Conversion......................................................... 355
Acknowledge Sequence ........................................... 206
Asynchronous Reception .......................................... 224
Asynchronous Transmission..................................... 222
Asynchronous Transmission
Automatic Baud Rate Calculation ............................. 220
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep .................... 225
Baud Rate Generator with Clock Arbitration ............. 200
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ............................................ 341
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start
(Back to Back) .................................................. 222
Normal Operation ............................................. 225
During Start Condition ...................................... 209
Condition (Case 1) ............................................ 210
Condition (Case 2) ............................................ 210
Condition (SCL = 0) .......................................... 209
PIC18F6525/6621/8525/8621
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision During Start
Bus Collision for Transmit and
Capture/Compare/PWM
CLKO and I/O ........................................................... 338
Clock Synchronization .............................................. 193
Clock/Instruction Cycle ............................................... 44
EUSART Synchronous
EUSART Synchronous
Example SPI Master Mode (CKE = 0) ...................... 345
Example SPI Master Mode (CKE = 1) ...................... 346
Example SPI Slave Mode (CKE = 0) ........................ 347
Example SPI Slave Mode (CKE = 1) ........................ 348
External Clock (All Modes Except PLL).................... 337
External Memory Bus Timing for Sleep
External Memory Bus Timing for TBLRD
External Memory Bus Timing for TBLRD
Full-Bridge PWM Output........................................... 165
Half-Bridge Output.................................................... 163
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect .................................................. 256
Master SSP I
Master SSP I
Parallel Slave Port (PSP) ......................................... 344
Parallel Slave Port (PSP) Read................................ 130
Parallel Slave Port (PSP) Write ................................ 129
Program Memory Read ............................................ 339
Program Memory Write ............................................ 340
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ............................................ 167
PWM Direction Change at Near
PWM Output ............................................................. 154
Repeated Start Condition ......................................... 202
Reset, Watchdog Timer (WDT),
Send Break Character Sequence............................. 226
Slave Mode General Call Address Sequence
2
2
2
2
2
2
2
2
2
2
2
C Bus Data............................................................. 349
C Bus Start/Stop Bits ............................................. 349
C Master Mode
C Master Mode (7-Bit Reception) .......................... 205
C Master Mode First Start Bit Timing ..................... 201
C Slave Mode (10-Bit Reception, SEN = 0) ........... 190
C Slave Mode (10-Bit Reception, SEN = 1) ........... 195
C Slave Mode (10-Bit Transmission) ..................... 191
C Slave Mode (7-Bit Reception, SEN = 0) ............. 188
C Slave Mode (7-Bit Reception, SEN = 1) ............. 194
C Slave Mode (7-Bit Transmission) ....................... 189
Condition (Case 1)............................................ 211
Condition (Case 2)............................................ 211
Condition (SDA Only) ....................................... 208
Acknowledge .................................................... 207
(All ECCP/CCP Modules) ................................. 343
Receive (Master/Slave) .................................... 353
Transmission (Master/Slave)............................ 353
(Microprocessor Mode)....................................... 77
(Extended Microcontroller Mode) ....................... 76
(Microprocessor Mode)....................................... 76
(7 or 10-Bit Transmission) ................................ 204
Auto-Restart Disabled) ..................................... 170
Auto-Restart Enabled) ...................................... 170
100% Duty Cycle .............................................. 167
Oscillator Start-up Timer (OST)
and Power-up Timer (PWRT) ........................... 341
(7 or 10-Bit Address Mode) .............................. 196
2
2
C Bus Data ........................................ 351
C Bus Start/Stop Bits ......................... 351
DS39612B-page 389