C8051F523A-IM Silicon Laboratories Inc, C8051F523A-IM Datasheet - Page 133

• Manufacturer Part Number: C8051F523A-IM
• Description: IC 8051 MCU 4K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F523A-IM

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1491-5

SFR Definition 13.13. P0SKIP: Port0 Skip
SFR Definition 13.14. P1MAT: Port1 Match
SFR Definition 13.15. P1MASK: Port1 Mask
Bits7–0: P1MAT[7:0]: Port1 Match Value.
Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
Bits7–0: P1MASK[7:0]: Port1 Mask Value.
R/W
R/W
Bit7
R/W
Bit7
Bit7
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK).
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (V
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
These bits select which Port pins will be compared to the value stored in P1MAT.
0: Corresponding P1.n pin is ignored and cannot cause a Port Match event.
1: Corresponding P1.n pin is compared to the corresponding bit in P1MAT.
R/W
R/W
Bit6
R/W
Bit6
Bit6
R/W
R/W
Bit5
R/W
Bit5
Bit5
R/W
Bit4
R/W
R/W
Bit4
Bit4
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
R/W
R/W
Bit3
R/W
Bit3
Bit3
R/W
R/W
Bit2
R/W
Bit2
Bit2
R/W
R/W
Bit1
R/W
Bit1
Bit1
REF
SFR Address:
SFR Address:
SFR Address:
input, external oscil-
R/W
Bit0
R/W
R/W
Bit0
Bit0
Reset Value
00000000
Reset Value
00000000
11111111
Reset Value
0xCF
0xBF
0xD4
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