AT90PWM3-16SQ Atmel, AT90PWM3-16SQ Datasheet - Page 220

• Manufacturer Part Number: AT90PWM3-16SQ
• Description: IC AVR MCU FLASH 8K 32SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16SQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.5.5.1
19.5.5.2
19.6
19.6.1
19.6.2
19.6.2.1
19.6.2.2
220
EUSART Registers Description
AT90PWM2/3/2B/3B
USART I/O Data Register – UDR
EUSART I/O Data Register – EUDR
Parity Checker
OverRun
UDR/EUDR data access with character size up to 8 bits
UDR/EUDR data access with 9 bits per character
All the receiver error flags are valid only when the RxC bit is set and until the UDR register is
read.
The parity checker of the EUSART is available only when data bits are level encoded and
behaves as is USART mode (See Parity checker of the USART).
The Data OverRun (DOR bit of USCRA) flag indicates data loss due to a receiver buffer full con-
dition. This flag operates as in USART mode (See USART section).
• Bit 7:0 – RxB7:0: Receive Data Buffer (read access)
• Bit 7:0 – TxB7:0: Transmit Data Buffer (write access)
This register is common to the USART and EUSART interfaces for Transmit Data Buffer Regis-
ter and Receive Data Buffer Register. See description for UDR register in USART.
• Bit 7:0 – RxB15:8: Receive Data Buffer (read access)
• Bit 7:0 – TxB15:8: Transmit Data Buffer (write access)
This register provide an extension to the UDR register when EUSART is used with more than 8
bits.
When the EUSART is used with 8 or less bits, only the UDR register is used for dta access.
When the EUSART is used with 9 bits character, the behavior is different of the standart USART
mode, the UDR register is used in combinaison with the first bit of EUDR (EUDR:0) for data
access, the RxB8/TxB8 bit is not used.
Initial Value
Initial Value
Read/Write
Read/Write
Bit
Bit
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
RXB[15:8]
TXB[15:8]
RXB[7:0]
TXB[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
1
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
4317J–AVR–08/10
EUDR (Read)
EUDR (Write)
UDR (Write)
UDR (Read)