AT90PWM3-16MQT Atmel, AT90PWM3-16MQT Datasheet

Page 1

... Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90PWM2 AT90PWM3 AT90PWM2B AT90PWM3B Summary 4317IS–AVR–01/08 ...

Page 2

... History Product AT90PWM2 AT90PWM3 AT90PWM2B AT90PWM3B This datasheet deals with product characteristics of AT90PW2 and AT90WM3. It will be updated as soon as characterization will be done. 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized ...

Page 3

... PB6 (ADC7/ICP1B PB5 (ADC6/INT2 PB4 (AMP0+) PB3 (AMP0 AREF 7 18 GND AVCC PB2 (ADC5/INT1 PD7 (ACMP0 PD6 (ADC3/ACMPM/INT0) PD5 (ADC2/ACMP2 AT90PWM3/3B SOIC 32 32 PB7(ADC4/PSCOUT01/SCK PB6 (ADC7/PSCOUT11/ICP1B PB5 (ADC6/INT2 PC7 (D2A PB4 (AMP0 PB3 (AMP0 PC6 (ADC10/ACMP1 AREF 8 24 GND 9 23 AVCC 10 22 ...

Page 4

... PD3 3.1 Pin Descriptions : Table 3-1. Pin out description S024 Pin SO32 Pin QFN32 Pin Number Number Number AT90PWM2/3/2B/3B 4 QFN32 (7*7 mm) Package. AT90PWM3/3B QFN (PSCIN1/OC1B) PC1 3 VCC 4 GND 5 (T0/PSCOUT22) PC2 6 (T1/PSCOUT23) PC3 7 (MISO/PSCOUT20) PB0 8 Mnemonic Type GND Power Ground: 0V reference AGND ...

Page 5

Table 3-1. Pin out description (Continued) S024 Pin SO32 Pin QFN32 Pin Number Number Number ...

Page 6

Table 3-1. Pin out description (Continued) S024 Pin SO32 Pin QFN32 Pin Number Number Number ...

Page 7

Block Diagram Figure 4-1. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in ...

Page 8

... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90PWM2 powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90PWM2/3 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits ...

Page 9

Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D ...

Page 10

Register Summary Address Name Bit 7 (0xFF) PICR2H (0xFE) PICR2L (0xFD) PFRC2B PCAE2B (0xFC) PFRC2A PCAE2A (0xFB) PCTL2 PPRE21 (0xFA) PCNF2 PFIFTY2 (0xF9) OCR2RBH (0xF8) OCR2RBL (0xF7) OCR2SBH (0xF6) OCR2SBL (0xF5) OCR2RAH (0xF4) OCR2RAL (0xF3) OCR2SAH (0xF2) OCR2SAL (0xF1) ...

Page 11

Address Name Bit 7 (0xBE) Reserved – (0xBD) Reserved – (0xBC) Reserved – (0xBB) Reserved – Reserved (0xBA) – Reserved (0xB9) – (0xB8) Reserved – (0xB7) Reserved – (0xB6) Reserved – (0xB5) Reserved – (0xB4) Reserved – (0xB3) Reserved – ...

Page 12

Address Name Bit 7 (0x7C) ADMUX REFS1 (0x7B) ADCSRB ADHSM (0x7A) ADCSRA ADEN (0x79) ADCH - / ADC9 (0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 (0x77) AMP1CSR AMP1EN (0x76) AMP0CSR AMP0EN (0x75) Reserved – (0x74) Reserved – (0x73) Reserved ...

Page 13

Address Name Bit 7 0x1A (0x3A) GPIOR2 GPIOR27 0x19 (0x39) GPIOR1 GPIOR17 0x18 (0x38) Reserved – 0x17 (0x37) Reserved – TIFR1 0x16 (0x36) – TIFR0 0x15 (0x35) – 0x14 (0x34) Reserved – 0x13 (0x33) Reserved – 0x12 (0x32) Reserved – ...

Page 14

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr ADC Rd, Rr ADIW Rdl,K SUB Rd, Rr SUBI Rd, K SBC Rd, Rr SBCI Rd, K SBIW Rdl,K AND Rd, Rr ANDI Rd Rd, ...

Page 15

Mnemonics Operands BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI ...

Page 16

Mnemonics Operands NOP SLEEP WDR BREAK AT90PWM2/3/2B/3B 16 Description No Operation Sleep (see specific descr. for Sleep function) Watchdog Reset (see specific descr. for WDR/timer) Break For On-chip Debug Only Operation Flags #Clocks None None None None 4317IS–AVR–01/ ...

Page 17

... Note: PWM2 is not recommended for new designs, use PWM2B for your developments Note: PWM3 is not recommended for new designs, use PWM3B for your developments 4317IS–AVR–01/08 Ordering Code Package AT90PWM3-16SQ SO32 AT90PWM3-16MQT QFN32 AT90PWM2-16SQ SO24 AT90PWM3B-16SE SO32 AT90PWM3B-16ME QFN32 AT90PWM2B-16SE ...

Page 18

Package Information SO24 24-Lead, Small Outline Package SO32 32-Lead, Small Outline Package QFN32 32-Lead, Quad Flat No lead AT90PWM2/3/2B/3B 18 Package Type 4317IS–AVR–01/08 ...

Page 19

SO24 4317IS–AVR–01/08 AT90PWM2/3/2B/3B 19 ...

Page 20

SO32 AT90PWM2/3/2B/3B 20 4317IS–AVR–01/08 ...

Page 21

QFN32 4317IS–AVR–01/08 AT90PWM2/3/2B/3B 21 ...

Page 22

AT90PWM2/3/2B/3B 22 4317IS–AVR–01/08 ...

Page 23

Errata 9.1 AT90PWM2&3 Rev. A (Mask Revision) • PGM: PSCxRB Fuse • PSC: Prescaler • PSC: PAOCnA and PAOCnB Register Bits (Asynchronous output control) • PSC: PEVxA/B Flag Bits • PSC: Output Polarity in Centered Mode • PSC: Output ...

Page 24

PSC: Output Polarity in Centered Mode In centered mode, PSCOUTn1 outputs are not inverted, so they are active at the same time as PSCOUTn0. Workaround: Use an external inverter (or a driver with inverting output) to drive the load ...

Page 25

The comparator output toggles at the comparator clock frequency when the voltage differ- ence between both inputs is lower than the offset. This may occur when comparing signal with small slew rate. Work around: This effect normally do not impact ...

Page 26

Use, when Vcc=5V, Vref below Vcc-1V. Or, when Vref=Vcc=5V, do not uses codes above 800. 4. DAC Update in Autotrig mode If the cpu writes in DACH register at the same instant that the selected trigger source occurs and DAC ...

Page 27

Datasheet Revision History for AT90PWM2/2B/3/3B Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 10.1 Changes from 4317A- to 4317B 1. ...

Page 28

PSC : the Balance Flank Width Modulation is done On-Time 1 rather than On-Time 0 (correction of figures) 4. Updated 5. Update of the 10.8 Changes from 4317H to 4317I 1. Updated 2. Updated 3. Updated 4. Updated 5. ...

Page 29

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...