C8051F344-GQ Silicon Laboratories Inc, C8051F344-GQ Datasheet - Page 68

IC 8051 MCU FLASH 64K 48TQFP

C8051F344-GQ

Manufacturer Part Number
C8051F344-GQ
Description
IC 8051 MCU FLASH 64K 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheets

Specifications of C8051F344-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 20x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
5.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
17-ch x 10-bit
No. Of I/o's
40
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
48TQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1452 - ADAPTER PROGRAM TOOLSTICK F340
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1302

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QSET
Q
Cross bar
Interrupt
Q
Q
(S
GND
CPn +
CPn -
CPnEN
CPnOUT
CPnRIF
CPnFIF
CPnHYP1
CPnHYP0
CPnHYN1
CPnHYN0
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
CPn
CPnACPn
CMX n N1
CMX n N0
CM XnP1
CM XnP0
CMX n N2
CM XnP2
P ort I/O connect ion options vary wit h packa ge (32-pin or 48-pin)
YNCHRO NIZER)
SET
C8051F340/1/2/3/4/5/6/7/8/9
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and supply current falls to less than 100 nA. See
page 159
externally driven from –0.25 V to (V
trical specifications are given in Table 7.1.
Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition
7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current. See
Table 7.1 for complete timing and supply current specifications.
68
CPTnMX
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
Figure 7.1. Comparator Functional Block Diagram
DD
) + 0.25 V without damage or upset. The complete Comparator elec-
Rev. 1.1
+
-
VDD
Section “15.1. Priority Crossbar Decoder” on
Reset Decision Tree
(Comprator 0 Only)

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