C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 237
C8051F321-GMR
Manufacturer Part Number
C8051F321-GMR
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Specifications of C8051F321-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART, USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F320DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel / 10 bit, 7 Channel
Package
28MLP
Device Core
8051
Family Name
C8051F321
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
For Use With
336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F321-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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20.3.1. Watchdog Timer Operation
While the WDT is enabled:
•
•
•
•
•
•
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is loaded
into PCA0CPH4 (See Figure 20.10).
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2-CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 4 is forced into Watchdog Timer mode.
Writes to the Module 4 mode register (PCA0CPM4) are disabled.
PCA0CPL4
C
D
L
I
Figure 20.10. PCA Module 4 with Watchdog Timer Enabled
W
D
E
T
PCA0MD
W
D
C
K
L
PCA0CPH4
C
P
S
2
Write to
C
P
S
1
C
P
S
0
E
C
F
8-bit Adder
Enable
Adder
Enable
Rev. 1.4
PCA0CPH4
Comparator
PCA0H
8-bit
Match
PCA0L Overflow
C8051F320/1
Reset
237
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