C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 135

• Manufacturer Part Number: C8051F321-GMR
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel / 10 bit, 7 Channel
• Package: 28MLP
• Device Core: 8051
• Family Name: C8051F321
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Bits7–0: P2.[7:0]
Note: P2.7–P2.4 only available on C8051F320 devices. Writes to these Ports do not require
Bits7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis-
Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
P2.7
R/W
R/W
R/W
Bit7
Bit7
Bit7
ter P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port
pin when configured as digital input.
0: P2.n pin is logic low.
1: P2.n pin is logic high.
XBARE = ‘1’.
SFR Definition 14.9. P1MDOUT: Port1 Output Mode Register
P2.6
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 14.10. P1SKIP: Port1 Skip Register
SFR Definition 14.11. P2: Port2 Register
P2.5
R/W
R/W
R/W
Bit5
Bit5
Bit5
P2.4
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.4
P2.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
P2.2
R/W
R/W
R/W
Bit2
Bit2
Bit2
P2.1
R/W
R/W
R/W
Bit1
Bit1
Bit1
C8051F320/1
(bit addressable)
P2.0
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
00000000
Reset Value
00000000
Reset Value
Reset Value
11111111
Address:
0xA5
0xA0
0xD5
SFR
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