C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 200

• Manufacturer Part Number: C8051F321-GMR
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel / 10 bit, 7 Channel
• Package: 28MLP
• Device Core: 8051
• Family Name: C8051F321
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F320/1
slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex
operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave
mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK,
NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less
than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to
the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can
receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided
that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.
200
NSS (Must Remain High
in Multi-Master Mode)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MISO
NSS (4-Wire Mode)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0)
Figure 18.5. Master Mode Data/Clock Timing
MSB
MSB
MSB
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Rev. 1.4
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 0
Bit 0
Bit 0