PIC18F442-I/PT Microchip Technology, PIC18F442-I/PT Datasheet - Page 246

• Manufacturer Part Number: PIC18F442-I/PT
• Description: IC MCU FLASH 8KX16 EE A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F442-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18FXX2
RLNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39564C-page 244
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register 'f'
Rotate Left f (no carry)
[ label ]
0
d
a
(f<n>)
(f<7>)
N, Z
The contents of register 'f' are
rotated one bit to the left. If 'd' is 0,
the result is placed in W. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLNCF
Read
Q2
0100
1010 1011
0101 0111
f
[0,1]
[0,1]
255
dest<n+1>,
dest<0>
RLNCF
01da
Process
REG, 1, 0
Data
Q3
register f
ffff
f [,d [,a]
destination
Write to
Q4
ffff
RRCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register 'f'
Rotate Right f through Carry
[ label ]
0
d
a
(f<n>)
(f<0>)
(C)
C, N, Z
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in W. If 'd' is 1, the result
is placed back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR value (default).
1
1
RRCF
Read
0011
Q2
1110 0110
0
1110 0110
0111 0011
0
f
[0,1]
[0,1]
© 2006 Microchip Technology Inc.
C
dest<7>
255
dest<n-1>,
C,
RRCF
00da
Process
REG, 0, 0
Data
register f
Q3
f [,d [,a]
ffff
destination
Write to
Q4
ffff