PIC18F442-I/PT Microchip Technology, PIC18F442-I/PT Datasheet - Page 165

• Manufacturer Part Number: PIC18F442-I/PT
• Description: IC MCU FLASH 8KX16 EE A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F442-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

15.4.17.3
Bus collision occurs during a STOP condition if:
a)
b)
FIGURE 15-31:
FIGURE 15-32:
© 2006 Microchip Technology Inc.
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is
sampled low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
Bus Collision During a STOP
Condition
P
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
Assert SDA
T
SDA asserted low
BRG
T
BRG
T
BRG
T
BRG
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0' (Figure 15-31). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data '0' (Figure 15-32).
SCL goes low before SDA goes high
Set BCLIF
T
BRG
T
BRG
PIC18FXX2
'0'
'0'
DS39564C-page 163
SDA sampled
low after T
Set BCLIF
'0'
'0'
BRG
,